Reliability Prediction From Burn-in Data Fit To Reliability Models

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Reliability Prediction From Burn-in Data Fit To Reliability Models

by Joseph Bernstein

Academic Press | March 10, 2014 | Hardcover

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This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design. " The ability to include reliability calculations and test results in their product design" The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions" Have accurate failure rate calculations for calculating warrantee period replacement costs.

Format: Hardcover

Dimensions: 108 pages, 9.41 × 7.24 × 0.98 in

Published: March 10, 2014

Publisher: Academic Press

Language: English

The following ISBNs are associated with this title:

ISBN - 10: 0128007478

ISBN - 13: 9780128007471

Found in: Science and Nature

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– More About This Product –

Reliability Prediction From Burn-in Data Fit To Reliability Models

by Joseph Bernstein

Format: Hardcover

Dimensions: 108 pages, 9.41 × 7.24 × 0.98 in

Published: March 10, 2014

Publisher: Academic Press

Language: English

The following ISBNs are associated with this title:

ISBN - 10: 0128007478

ISBN - 13: 9780128007471

Table of Contents

Introduction
1. Shortcut to accurate reliability prediction
2. M-HTOL Principles
3. Failure Mechanisms
4. New M-HTOL Approach
5. Bibliography

From the Publisher

This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design. " The ability to include reliability calculations and test results in their product design" The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions" Have accurate failure rate calculations for calculating warrantee period replacement costs.

From the Jacket

This work will educate chip and system designers in a method for accurately predicting circuit and system reliability in order to estimate failures that will occur as a function of operating conditions at the chip level. Currently, chip suppliers perform HTOL end-of-life testing as part of their standard qualification procedure, and make accurate reliability predictions based on this. However, this knowledge is often presented to designers and manufacturers with little explanation of how to use it in a meaningful, practical way. This book combines the knowledge found in many reliability publications and illustrates how to use the information presented by semiconductor manufacturing companies and chip suppliers, and make accurate reliability predictions. It allows chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature, to include reliability calculations and test results in their designs, to make meaningful reliability predictions, and to make accurate failure rate calculations for warranty period replacement costs. All of this also means that users will ultimately have control of reliability and performance in their design.

The book is aimed at chip designers and manufacturers, electronic and microelectronic system designers and reliability engineers in electronics companies. It will also be of value to academics and researchers studying microelectronics failure mechanisms.

About the Author

Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.
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