Adiabatic Logic: Future Trend and System Level Perspective by Philip TeichmannAdiabatic Logic: Future Trend and System Level Perspective by Philip Teichmann

Adiabatic Logic: Future Trend and System Level Perspective

byPhilip Teichmann

Hardcover | October 30, 2011

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Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.
Philip Teichmann studied electrical engineering at the Technische Universität München with a focus on the physics of electronic devices and microelectronics. During his work at the Institute of Technical Electronics at the Technische Univeristät München he focused on the design of circuits for ultra low-power energy consumption. He has...
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Title:Adiabatic Logic: Future Trend and System Level PerspectiveFormat:HardcoverDimensions:183 pagesPublished:October 30, 2011Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:940072344X

ISBN - 13:9789400723443

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Table of Contents

1 Introduction. 1.1 Motivation for this work. 1.2 A brief history of reversible computation and Adiabatic Logic.   2 Fundamentals of Adiabatic Logic. 2.1 Charging process in AL compared to static CMOS. 2.2 An adiabatic system. 2.3 Loss mechanisms in Adiabatic Logic. 2.4 Voltage scaling ­ A comparison of static CMOS and AL. 2.5 Properties and design considerations in AL. 2.6 General simulation setup. 3 Future trend in Adiabatic Logic. 3.1 Scaling trends for sub 90nm transistors. 3.2 Adiabatic Logic with novel devices. 3.3 NBTI and HCI in Adiabatic Logic. 4 Generation of the power-clock. 4.1 Introduction. 4.2 Topologies of inductor­based power­clock generators. 4.3 Impact of pattern-­induced variations. 4.4 Generation of the synchronization signals. 5 Power-Clock Gating. 5.1 Introduction to Power­-Clock Gating. 5.2 The theory of Power-­Clock Gating. 5.3 Gating topologies for PCG. 5.4 Power­-down mode for the synchronous 2N2P LC­oscillator. 6 Arithmetic structures in Adiabatic Logic. 6.1 Design of arithmetic structures. 6.2 Overhead reduction by applying complex gates. 6.3 Multi­-operand adders and the CORDIC algorithm. 7 Measurement results of an adiabatic FIR filter. 7.1 Structure of the adiabatic FIR filter. 7.2 Measurement results and comparison to static CMOS. 8 Conclusions.