Advanced Hdl Synthesis And Soc Prototyping: Rtl Design Using Verilog by Vaibbhav TaraateAdvanced Hdl Synthesis And Soc Prototyping: Rtl Design Using Verilog by Vaibbhav Taraate

Advanced Hdl Synthesis And Soc Prototyping: Rtl Design Using Verilog

byVaibbhav Taraate

Hardcover | January 18, 2019

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This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
Vaibbhav Taraate is an Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology Bombay (...
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Title:Advanced Hdl Synthesis And Soc Prototyping: Rtl Design Using VerilogFormat:HardcoverDimensions:307 pages, 23.5 × 15.5 × 2.49 inPublished:January 18, 2019Publisher:Springer NatureLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:981108775X

ISBN - 13:9789811087752

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Table of Contents

Introduction.- SOC Design.- RTL Design Guidelines.- RTL Design and Verification.- Processor cores and Architecture design.- Buses and protocols in SOC designs.- DSP Algorithms and Video Processing.- ASIC and FPGA Synthesis.- Static Timing Analysis.- SOC Prototyping.- SOC Prototyping guidelines.- Design Integration and SOC synthesis.- Interconnect delays and Timing.- SOC Prototyping and debug techniques.- Testing at the board level.