CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test by Andrei PavlovCMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test by Andrei Pavlov

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design…

byAndrei Pavlov

Paperback | October 28, 2010

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As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Prof. Sachdev has authored several successful books with Springer
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Title:CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design…Format:PaperbackDimensions:212 pages, 9.25 × 6.1 × 0 inPublished:October 28, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:904817855X

ISBN - 13:9789048178551

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Table of Contents

Foreword. Preface. Acronyms. 1. INTRODUCTION AND MOTIVATION. 1.1 Motivation. 1.2 SRAM in the Computer Memory Hierarchy. 1.3 Technology Scaling and SRAM Design and Test. 1.4 SRAM test economics. 1.5 SRAM Design and Test Tradeoffs. 1.6 Redundancy.2. SRAM CIRCUIT DESIGN AND OPERATION. 2.1 Introduction. 2.2 SRAM block structure. 2.3 SRAM cell design. 2.4 Cell layout considerations. 2.5 Sense Amplifier and Bit Line Precharge-Equalization. 2.6 Write Driver. 2.7 Row Address Decoder and Column MUX. 2.8 Address Transition Detector. 2.9 Timing Control Schemes. 2.10 Summary.3. SRAM CELL STABILITY: DEFINITION, MODELING AND TESTING. 3.1 Introduction. 3.2 Static noise margin of SRAM cells. 3.3 SNM Definitions. 3.4 Analytical expressions for SNM calculations. 3.5 SRAM cell stability sensitivity factors. 3.6 SRAM cell stability fault model. 3.7 SRAM Cell Stability Detection Concept. 3.8 March tests and stability fault detection in SRAMs. 3.9 Summary.4. TRADITIONAL SRAM FAULT MODELS AND TEST PRACTICES. 4.1 Introduction. 4.2 Traditional fault models. 4.3 Traditional SRAM test practices. 4.4 Summary.5. TECHNIQUES FOR DETECTION OF SRAM CELLS WITH STABILITY FAULTS. 5.1 Introduction. 5.2 Classification of SRAM cell stability test techniques. 5.3 Passive SRAM Cell Stability Test Techniques. 5.4 Active SRAM Cell Stability Test Techniques. 5.5 Summary.6. SOFT ERROR IN SRAMs: SOURCES, MECHANISM AND MITIGATION TECHNIQUES. 6.1 Introduction. 6.2 Soft Error Mechanism. 6.3 Sources of Soft Errors. 6.4 Soft Errors and Defects in the Pull-Up Path of a Cell. 6.5 Soft Error Mitigation Techniques. 6.6 Leakage-Reduction Techniques and the SER. 6.7 Summary. References. Index.