Co-verification of Hardware and Software for ARM SoC Design

Other | September 1, 2004

byAndrews, Jason, Jason Andrews

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Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing.

This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.

* The only book on verification for systems-on-a-chip (SoC) on the market

* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes

* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs

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From the Publisher

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly ...

Jason Andrewsis currently working in the areas of hardware/software co-verification and testbench methodology for SoC design at Verisity. He has implemented multiple commercial co-verification tools as well as many custom co-verification solutions. His experience in the EDA and embedded marketplace includes software development and pro...

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Format:OtherDimensions:288 pages, 1 × 1 × 1 inPublished:September 1, 2004Publisher:NewnesLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0080476902

ISBN - 13:9780080476902

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Extra Content

Table of Contents

1. Embedded System Verification
2. Hardware and Software Design Process: System initialization software and hardware abstraction layer (HAL), Hardware diagnostic test suite, Real-time operating system (RTOS), RTOS device drivers, Application software, C simulation, Logic simulation, Simulation acceleration, Emulation, Prototype;
3. SoC Verification Topics for the ARM Architecture;
4. Hardware/Software Co-Verification: Host-code execution - implicit access, ISS + BIM, CCM, RTL, Hardware model,Emulation board, FPGA Prototype;
5. Advanced Hardware/Software Co-Verification: Direct access to simulation memories without advancing simulation time, Memory and time optimizations - understanding synchronization, Cross network connections versus using a single workstation, C modeling for some of the hardware, Implicit Access,Post-processing techniques for software debugging, Synchronized software and hardware views for debugging, Post-processing software trace, Save/restore, How to deal with peripherals, How to deal with an RTOS;
6. Hardware Verification Environment and
Co-Verification: Testbench, The use of testbench tools, Random test generation based on CPU address map, CPU bus protocol checking, Functional/ Transaction coverage, Memory coverage, Property checking - did a specific scenario ever happen? Use of a design signoff model;
7. Methodology for an Example ARM SoC.