Computer Aided Verification: 5th International Conference, CAV'93, Elounda, Greece, June 28 - July 1, 1993. Proceedings by Costas CourcoubetisComputer Aided Verification: 5th International Conference, CAV'93, Elounda, Greece, June 28 - July 1, 1993. Proceedings by Costas Courcoubetis

Computer Aided Verification: 5th International Conference, CAV'93, Elounda, Greece, June 28 - July…

EditorCostas Courcoubetis

Paperback | June 16, 1993

Pricing and Purchase Info

$159.25 online 
$180.95 list price save 11%
Earn 796 plum® points

Prices and offers may vary in store

Quantity:

In stock online

Ships free on orders over $25

Not available in stores

about

This volume contains the proceedings of the Fifth Conferenceon Computer-Aided Verfication, held in Crete, Greece, inJune/July 1993.The objective of the CAV conferences is to bring togetherresearchers and practitioners interested in the developmentanduse of methods, tools, and theories for thecomputer-aided verification of concurrent systems. Theconferences provide an opportunity for comparing variousverfication methods and tools that can be used to assist theapplications designer. Emphasis is placed on new researchresults and the application of existing methods to realverification problems.The volume contains abstracts of three invited lectures andfull versions of 37 contributed papers selected from 84submissions.The contributions are grouped into sections onhardware verification with BDDs, methods and tools, theoremproving, analysis of real-time systems, process algebras andcalculi, partial orders, and exploiting symmetry.
Title:Computer Aided Verification: 5th International Conference, CAV'93, Elounda, Greece, June 28 - July…Format:PaperbackDimensions:520 pagesPublished:June 16, 1993Publisher:Springer Berlin HeidelbergLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:3540569227

ISBN - 13:9783540569220

Look for similar items by category:

Reviews

Table of Contents

Logic synthesis and design verification.- Efficient verification with BDDs using implicitly conjoined invariants.- Parametric circuit representation using inductive Boolean functions.- An iterative approach to language containment.- BDD-Based debugging of designs using language containment and fair CTL.- Reliable hashing without collision detection.- A tool for symbolic program verification and abstraction.- Symbolic equivalence checking.- A decision algorithm for full propositional temporal logic.- Reachability and recurrence in Extended Finite State Machines: Modular Vector Addition Systems.- Automatic generation of network invariants for the verification of iterative sequential systems.- A Graphical Interval Logic toolset for verifying concurrent systems.- Combining model checking and theorem proving to verify parallel processes.- Verification of a multiplier: 64 bits and beyond.- Protocol design for an automated highway system.- Computing accumulated delays in real-time systems.- Reachability analysis of planar multi-linear systems.- An efficient algorithm for minimizing real-time transition systems.- Verification of timing properties of VHDL.- Alternating RQ timed automata.- Timed modal specification - Theory and tools.- A mechanically verified application for a mechanically verified environment.- Verification of real-time systems using PVS.- The formal verification of an algorithm for interactive consistency under a hybrid fault model.- Computer-assisted simulation proofs.- A verifier and timing analyser for simple imperative programs.- Efficient verification of parallel real-time systems.- Delay analysis in synchronous programs.- Verifying quantitative real-time properties of synchronous programs.- A modal logic for message passing processes.- Functionality decomposition by compositional correctness preserving transformation.- On model-checking for fragments of ?-calculus.- On-the-fly verification with stubborn sets.- All from one, one for all: on model checking using representatives.- Verifying timed behavior automata with input/output critical races.- Refining dependencies improves partial-order verification methods (extended abstract).- Exploiting symmetry in temporal logic model checking.- Symmetry and model checking.- Generation of reduced models for checking fragments of CTL.- A Structural linearization principle for processes.