Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE by Rudy LauwereinsDesign, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE by Rudy Lauwereins

Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE

EditorRudy Lauwereins, Jan Madsen

Paperback | October 19, 2010

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In 2007 The Design, Automation and Test in Europe (DATE) conference celebrated its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.
Dr. Rudy Lauwereins is the General Chair for DATE 2007, Dr. Jan Madsen is the Technical Chair.
Title:Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATEFormat:PaperbackDimensions:528 pagesPublished:October 19, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048176530

ISBN - 13:9789048176533

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Table of Contents

Introduction; Rudy Lauwereins, Jan MadsenSection 1: System Level DesignIntroduction: System Level Design: Past, Present and Future; Daniel D. GajskiScheduling of Conditional Process Graphs for the Synthesis of Embedded Systems; P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop, DATE1998EXPRESSION: A language for architecture exploration through compiler/simulator retargetability; A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau, DATE1999RTOS Modeling For System Level Design; A. Gerstlauer, H. Yu, D.D. Gajski, DATE2003Context-aware performance analysis for efficient embedded system design; M. Jersak, R. Henia, R. Ernst, DATE2004On Lock-Free Synchronization for Dynamic Embedded Real-Time Software; H. Cho, .B Ravindran, E.D. Jensen, DATE2006What If You Could Design Tomorrow's System Today? N. Wingen, DATE2007Section 2: Networks on ChipIntroduction: Networks on Chip; Giovanni De MicheliA generic architecture for on-chip packet- switched interconnections; P. Guerrier, A. Greiner, DATE2000Trade Offs In The Design Of A Router With Both Guaranteed And Best-Effort Services For Networks On Chip; E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, DATE2003Exploiting The Routing Flexibility For Energy-Performance Aware Mapping Of Regular Noc Architectures; J. Hu, R. Marculescu, DATE2003xpipesCompiler: A tool for instantiating application specific Networks on Chip; A. Jalabert, S. Murali, L. Benini, G. De Micheli, DATE2004Network traffic generator model for fast network-on-chip simulation; S. Mahadevan, F. Angiolini, M. Storoaard, R.G. Olsen, J. Sparsoe, J. Madsen, DATE2005Section 3: Modeling, Simulation and Run-Time ManagementIntroduction: Modeling, Simulation and Run-Time Management; Enrico MaciiDynamic power management for non-stationary service requests; E.Y. Chung, L. Benini, A. Bogiolo, G. De Micheli, DATE1999Quantitative comparison of power management algorithms; Y. Lu, E. Chung, T. Simunic, L. Benini, G. De Micheli, DATE2000Energy efficiency of the IEEE 802.15. 4 standard in dense wireless microsensor networks: modeling and improvement perspectives; B. Bougard, F. Catthoor, D.C. Daly, A. Chandrakasan, W. Dehaene, DATE2005Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application; A. Singhee, R.A. Rutenbar, DATE2007Compositional Specification of Behavioral Semantics; K. Chen, J. Sztipanovits and S. Neem, DATE2007Section 4: Design technology for advanced digital systems in CMOS and beyondIntroduction: Design technology for advanced digital systems in CMOS and beyond; Hugo De ManAddress Bus Encoding Techniques for System-Level Power Optimization; L. Benini, G. De Micheli, E. Maccii, D. Sciuto, and C. Silvano, DATE1998MOCSYN: Multiobjective core-based single-chip system synthesis; R.P. Dick, N.K. Jha, DATE1999Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor; G. Quan and X. Hu, DATE2002Synthesis and optimization of threshold logic networks with application to nanotechnologies; R. Zhang, P. Gupta, L. Zhong, N.K. Jha, DATE2004Section 5: Physical design and validationIntroduction: Physical Design and Validation; Jochen JessInterconnect Tuning Strategies for High-Performance ICs; A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma, DATE1998Efficient Inductance Extraction Via Windowing; M.W. Beattie and L.T. Pileggi, DATE2001Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits; Y.S. Dhillon, A.U. Diril, A. Chatterjee, DATE2005A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology; C. Niclass, M. Sergio, E. Charbon, DATE2006Section 6: Test and verificationIntroduction: Test and Verification; T.W. Williams and R. KapurCost reduction and evaluation of a temporary faults detecting technique; L. Anghel, M. Nicolaidis, DATE2000An integrated system-on-chip test framework; E. Larsson, Z. Peng, DATE2001Efficient Spectral Techniques For Sequential ATPG; A. Giani, S. Sheng and M.S. Hsiao, DATE2001BerkMin: A Fast and Robust Sat-Solver; E. Goldberg and Y. Novikov, DATE2002Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression; P. Gonciari, B. Al-Hashimi, and N. Nicolici, DATE2002An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs; P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero,  M. Sonza Reorda, DATE2006Appendix: Shortlist of most influential papers per year.