Digital Electronics by G. K. KharateDigital Electronics by G. K. Kharate

Digital Electronics

byG. K. Kharate

Paperback | August 12, 2012

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Beginning with the fundamentals such as logic families, number systems, Boolean algebra and logic gates, and combinational circuits, the book proceeds on to cover the applied aspects like sequential logic, ASM, programmable logic devices, converters and semiconductor memories. All the chaptersin the book begin with outlining the contents of the chapters and include numerous solved examples and review questions to enhance the understanding of key concepts. Owing to its lucid style of presentation and a large number of numerical exercises and multiple choice questions at the end of the chapters, the book will also serve as a self-preparatory material for students.
Dr GK Kharate is currently Principal of Matoshri College of Engineering and Research Centre, Nashik. He is also a fellow member of Institution of Electronics and Telecommunication Engineers (IETE) and a life member of many other professional bodies of repute like Indian Society for Technical Education (ISTE), Institution of Engineers ...
Title:Digital ElectronicsFormat:PaperbackDimensions:640 pages, 9.49 × 6.3 × 1.19 inPublished:August 12, 2012Publisher:Oxford University PressLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0198061838

ISBN - 13:9780198061830


Table of Contents

1. LOGIC FAMILIES1.1. Introduction1.2. Logic Families1.3. Transistor as a Switch1.4. Characteristics of Digital ICs1.4.1. Speed of Operation1.4.2. Power Dissipation1.4.3. Figure of Merit1.4.4. Fan-out1.4.5. Fan-in1.4.6. Current and Voltage Parameters1.4.7. Noise Immunity1.4.8. Power Supply Requirements1.4.9. Operating Temperature1.5. Resistor - Transistor Logic (RTL)1.6. Direct Coupled Transistor Logic (DCTC)1.7. Diode - Transistor Logic (DTL)1.8. Modified Diode - Transistor Logic1.9. Transistor - Transistor Logic (TTL)1.9.1. TTL with passive pull-up1.9.2. TTL with totem - Pole output1.9.3. Wired and Connection1.9.4. TTL with open collector output1.9.5. Unconnected inputs of TTL1.9.6. Tri-State TTL1.10. TTL Parameters1.11. Commonly used ICs of Standard TTL1.12. Improved TTL series1.12.1. Low Power and High Speed TTL1.12.2. Schottky TTL1.12.3. Lower Power Schottky TTL1.13. Comparison of TTL families1.14. Emitter Coupled Logic1.14.1. ECL Characteristics1.15. Integrated Injection Logic (I2L)1.15.1. I2L Inverter1.15.2. I2L Nandgate1.15.3. I2L Nor gate1.16. MOSFET Logic1.17. NMOS1.17.1. MNOS Inverter1.17.2. NMOS NAND gate1.17.3. NMOS NOR gate1.17.4. Fan-out1.17.5. Propagation delay time1.17.6. Power dissipation1.18. CMOS1.18.1. CMOS inverter1.18.2. CMOS Nand gate1.18.3. CMOS NOR gate1.18.4. Characteristics of CMOS1.18.5. Buffered and Unbuffered gates1.18.6. Transmission gates1.18.7. Open drain outputs1.18.8. High impedance outputs1.18.9. Specifications and Standards1.19. Comparison of CMOS and TTL Families1.20. Interfacing CMOS and TTL Devices1.20.1. TTL Driving CMOS1.20.2. CMOS Driving TTL1.21. Interfacing of ECL and TTL devices1.21.1. TTL driving ECL1.21.2. ECL driving TTL1.22. Key terms and definitions1.23. Summary1.24. Exercise2. NUMBER SYSTEMS AND CODES2.1. Introduction2.2. Number Systems2.3. Interconversion of Numbers2.3.1. Binary to Decimal Conversion2.3.2. Decimal to Binary Conversion2.3.3. Octal to Decimal Conversion2.3.4. Decimal to Octal Conversion2.3.5. Octal to Binary Conversion2.3.6. Binary to Octal Conversion2.3.7. Hexadecimal to Decimal Conversion2.3.8. Decimal to Hexadecimal Conversion2.3.9. Hexadecimal to Binary Conversion2.3.10. Binary to Hexadecimal Conversion2.4. Signed Binary Number2.4.1. Sign-Magnitude Representation2.4.2. 1's Complement Representation2.4.3. 2's Complement Representation2.5. Floating Point Representation of Number2.6. Binary Arithmetic2.6.1. Binary Addition2.6.2. Binary Substraction2.6.3. Binary Multiplication2.6.4. Binary Division2.7. Complement Binary Arithmetic2.7.1. One's (1's) Compliment Arithmetic2.7.2. Two's (2's) Compliment Arithmetic2.8. Arithmetic Overflow2.9. Codes2.9.1. Classification of Codes2.9.2. BINARY Coded Decimal Code (BCD CODE) BCD Arithmetic2.9.3. 2-4-2-1 Code2.9.4. Four-Bit BCD Codes2.9.5. Five Bit BCD Codes2.9.6. Biquinary Code2.9.7. Excess-3 Code2.9.8. Gray Code2.9.8.1. Binary to Gray Code Conversion2.9.8.2. Gray to Binary Code Conversion2.9.9. Seven Segment Code2.9.10. Alphanumeric Codes2.9.10.1. ASCII Code2.9.10.2. EBCDIC Code2.9.11. Error Detecting Codes2.9.11.1. Parity Codes2.9.11.2. Block Parity Codes2.9.12. Error Correcting Codes2.9.12.1. Linear Block Code2.9.12.2. Hamming Code2.10. Solved Examples2.11. Summary2.12. Exercises2.13. Problems2.14. Objective Type Questions3. BOOLEAN ALGEBRA AND LOGIC GATES3.1. Introduction3.2. Boolean Algebra3.2.1. Principal of Logic Circuits3.2.2. Boolean Constants, Variables and functions3.2.3. Basic laws of Boolean Algebra3.2.4. Boolean Theorems3.3. Overview of Logic Circuit3.4. Demorgan's Theorems3.5. Standard Representation for logical functions3.5.1. Sum of products from3.5.2. Products of Sums3.6. Minterm and Maxterm3.7. Simplification of Boolean expression3.7.1. Algebraic method3.7.2. Karnaugh Map Simplification3.7.2.1. Representation of k-map3.7.2.2. Representation of truth table on K-map3.7.2.3. Representation of sum of products of K-map3.7.2.4. Representation of product of sum on K-map3.7.2.5 .Grouping the adjacent cells3.8. Simplification of sum of product expression3.9. Simplification of product of sums expression3.10. Don't Care Condition3.11. Five and Six Variable K-map3.12. Quine McCluskey method3.13. Summary3.14. Exercise3.15. Objective Type Questions4. COMBINATIONAL LOGIC CIRCUIT4.1. Introduction4.2. Design Procedure for Combinational Logic Circuit4.2.1. Examples of Combinational Logic Circuit4.3. Adders4.3.1. Half adder4.3.2. Full adder4.3.3. N-Bit Parallel Adder4.3.4. Carry Look Ahead Adder4.3.5 IC 74LS834.4. Subtractor4.4.1. Half subtractor4.4.2. Full subtractor4.4.3. N-Bit Parallel subtractor4.4.4. Four Bit subtractor Using Adder4.4.4.1. 1's Complement Subtraction4.4.4.2. 1's Complement Subtraction4.5. BCD Adder4.6. BCD Subtractor4.6.1. 9's complement4.6.2. 9's complement subtraction4.6.3. 10'scomplement4.6.4. 10's complement subtraction4.7. Arithmetic Logic Unit (ALU)4.8. Comparator4.8.1. IC 7485 [4 Bit-Comparator]4.9. Parity generator4.9.1. Even parity generator4.9.2. Odd parity generator4.10. Parity checker4.10.1. Even parity checker4.10.2. Odd parity checker4.11. Parity generator/checker (IC74180)4.12. Multiplexer4.12.1. Multiplexer Tree4.12.2. Multiplexer Applications4.13. Demultiplexer4.13.1. Demultiplexer Tree4.13.2. Demultiplexer Applications4.14. Code Converters4.14.1. Binary to BCD Converter4.14.2. BCD to Binary converter4.14.3. BCD to Excess - 34.14.4. Excess - 3 to BCD Code Converter4.14.5. Binary to Gray Code Converter4.14.6. Gray to Binary Code Converter4.14.7. BCD to Seven-Segment code converter4.14.8. BCD to Seven-Segment display decoder/Driver4.14.9. Basic connection for driving 7-segment displays4.12.10. ICs of Seven-segment Driver/Decoder4.15. PIN diagrams of ICs4.16. Key terms and definitions4.17. Exercise4.18. Objective Type Questions5. SEQUENTIAL LOGIC5.1. Introduction5.2. One bit Memory Cell5.2.1. One bit Memory Cell using Transistors5.2.2. One bit Memory Cell using NAND gates5.2.3. One bit Memory Cell using NOR gates5.3. Clocked S.R. Flip-flop5.3.1. Preset and Clear inputs5.4. J-K Flip-Flop5.4.1. Race-Around condition5.4.2. Master-Slave j-K Flip-Flop5.5. D Flip-Flop5.6. T Flip-Flop5.7. Edge Triggered Flip-Flop5.8. Characterstics of Flip-Flop5.8.1. Propagation Delay (tp)5.8.2. Set-up time (tg)5.8.3. Hold-up time (tn)5.8.4. Maximum check frequency (Fmax)5.8.5. Asynchronous Active Pulse Width5.8.6. Clock high pulse time and low pulse time5.9. Flip-Flop Conversion5.9.1. S-R. Flip-Flop to T Flip-Flop5.9.2. S-R. Flip-Flop to D Flip-Flop5.9.3. S-R. Flip-Flop to J.K. Flip-Flop5.9.4. T Flip-Flop to D Flip-Flop5.9.5. D Flip-Flop to T Flip-Flop5.9.6. J-K. Flip-Flop to T Flip-Flop5.9.7. J-K. Flip-Flop to D Flip-Flop5.10. Application of Flip-Flops5.10.1. Bounce Elimination Switch5.10.2. Registers5.10.3. Counters5.10.4. Random Access Memory5.11. Sequential Logic Design (Introduction)5.12. Registers and Shift registers5.12.1. Serial in serial out shift register5.12.2. Serial In parallel out shift register5.12.3. Parallel in serial out shift register5.12.4. Parallel In Parallel out shift register5.12.5. Bi-directional shift register5.12.6. Universal register5.13. Applications of Shift register5.13.1. Serial to parallel converter5.13.2. Parallel to serial converter5.13.3. Ring counter5.13.4. Johnson counter and Twisted Ring counter5.13.5. Sequence generator5.13.6. Sequence detector5.14. Commonly used ICs for Shift register5.15. Ripple counter5.15.1. Up/Down Asynchronous counter5.15.2. Modulus 'M' Asynchronous counter5.15.3. Commonly used ICs for Asynchronous counter5.16. Synchronous counter5.17. Flip-Flop Excitation table5.17.1. Excitation table of R-S flip-flop5.17.2. Excitation table of J-K flip-flop5.17.3. Excitation table of T flip-flop5.17.4. Excitation table of DT flip-flop5.18. Synchronous Counter Design5.19. UP/DOWN Counter5.19.1. Commonly used ICs for Synchronous Counter5.19.2. 741915.19.3. 741925.20. Clocked Sequential Circuit5.20.1. Moore Circuit5.20.2. Mealy Circuit5.21. Analysis of Clocked Sequential Circuit5.21.1. State Table5.21.2. State Diagram5.22. Design of Clocked Sequential Circuit5.22.1 State Table5.22.2. State Diagram5.22.3. State Reduction5.22.4. State Assignment5.23. Lockout Condition5.24. Sequence Generator5.25. Sequence Detector5.26. Summary5.27. Exercise5.28. Objective Type Questions6. ASYNCHRONOUS SEQUENTIAL CIRCUITS6.1. Introduction6.2. Design of Fundamental Mode Asynchronous Sequential Circuits6.2.1. Realization using D Flip-Flops6.2.2. Realization using JK Flip-Flops6.3. Design of Pulse Mode Asynchronous Sequential Circuits6.4. Incompletely Specified State Machines6.5. Problems in Asynchronous Circuits6.5.1. Cycles6.5.2. Races6.5.3. Hazards6.6. Design of Hazard Free Switching Circuits6.7. Summary6.8. Exercise6.9. Objective Type Questions7. ALGORITHMIC STATE MACHINES7.1. Introduction7.2. Algorithmic State Machines (ASM)7.2.1. State Box7.2.2. Decision Box7.2.3. Conditional Box7.2.4. ASM block7.3. Realization of ASM charts7.3.1. Traditional Synthesis from an ASM chart7.3.2. Multiplexer Controller method7.4. Solved problems on ASM charts7.5. Register transfer language7.6. RTL Notations7.6.1. Register Transfer statements7.6.1.1. Shift operation7.6.1.2. Rotate operation7.6.2. Logical Operation statement7.6.2.1. Inversion operation7.6.2.2. ANDing operation7.6.2.3. ORing operation7.6.3. Connection operation statement7.6.4. Branch statements7.6.4.1. Unconditional branch statement7.6.4.2. Conditional branch statement7.6.5. Conditional transfer statement7.6.6. Count statement7.6.7. Declaration statement7.6.8. BUS connection statement7.7. Data Unit Construction from an RTL Description7.8. VHDL7.8.1. Entity - Architecture pair7.8.2. Entity Declaration7.8.3. Architecture Body7.8.4. Structural Modeling7.8.4.1. Description of Full Adder Architecture7.8.4.2. Declarative part7.8.4.3. Statement part7.8.5. Data Flow Modeling7.8.5.1. WHEN - ELSE Statement7.8.5.2. With - Select Statement7.8.6. Behavioral Style of Modeling7.8.7. Sequential Statements used in behavioral modeling7.8.8. Mixed Style of Modeling7.8.9. Configurations7.8.9.1. Default Configurations7.8.9.2. Component Configuration7.8.10. Important Data Objects in VHDL7.8.10.1. Signal7.8.10.2. Variable7.8.10.3. Constant7.8.11. Important Data Types7.8.12. VHDL Operators7.8.13. VHDL Examples7.9. Summary7.11. Exercise8. PROGRAMMABLE LOGIC DEVICES8.1. Introduction8.2. Programmable Logic Array8.2.1. Internal diagram of PLA8.2.1.1. Input Buffer8.2.1.2. AND matrix8.2.1.3. OR matrix8.2.1.3. Invert/Non-invert matrix8.2.1.4. Output Buffer8.2.2. Combinational Logic Design using PLA8.2.3. Sequential Logic Design using PLA8.3. Programmable Array Logic8.3.1. Internal diagram of PAL8.3.2. Registered Output PALs8.3.3. Configurable PALs8.3.4. Combinational Logic design using PALs8.3.5. Sequential Logic design using PAL8.4. Generic Array Logic Devices (GALs)8.4.1. Architecture of GAL 16V88.5. Classification of PLDs8.6. Complex Programmable Logic Devices8.6.1. Xilinx XC 9500 CPLD family8.6.1.1. Internal Architecture8.6.1.2. Function - Block Architecture8.6.1.3. I/O Block of XC 95008.6.1.4. Switch Matrix8.7. Field Programmable Gate Array8.7.1. Xilinx FPGA Architecture8.7.1.1. Configurable Logic Block8.7.1.2. Combinational Function Generator8.7.1.3. Flip-Flop8.7.1.4. Programmable Multiplexers8.7.1.5. Input-Output Block (IOB) Switching Matrix Structure8.7.2. XC 4000 Series FPGA8.7.2.1. Configurable Logic Block of XC 4008.7.2.2. Input - Output Mock of XC 40008.7.2.3. Programmable Interconnects8.8. Application Specific Integrated Circuits (ASICs)8.8.1. Full Custom ASICs8.8.2. Semi-Custom ASICs8.8.2.1. Standard Cell Based ASICs8.8.2.2. Gate Array Based ASICs8.9. Solved Examples8.10. Summary8.11. Exercises9. CONVERTERS9.1. Introduction9.2. Basic Principle of D/A Converter9.2.1. Digital to Analog (D/A) converter circuits9.2.2. Digital to Analog Converter9.2.3. Specifications of D/A converter9.2.4. Basic principle of Analog to Digital converter9.3.1. Analog to Digital converter circuits9.3.2. Parallel Comparator Analog to Digital Converter (Flash Converter)9.3.3. Successive-approximation A/D converter9.3.4. Dual slope A/D converter9.3.5. Specifications for Analog to Digital Converter9.4. D/A and A/D Converter ICs9.5. ADC 0809 (8 bit A/D converter)9.6. ADC-7109 (12 Bit binary A/D converter)9.7. DAC 0808 (8-bit D/A converter)9.8. Solved Examples9.9. Summary9.10. Exercises10. SEMICONDUCTOR MEMORIES10.1. Introduction10.2. Memory Organization10.3. Functional Diagram of Memory10.4. Memory Operations10.5. Expanding Memory Size10.5.1. Expanding Word Size10.5.2. Expanding word capacity10.5.3. Expanding Of Word Size and Word Capacity10.6. Characteristics of Memory Devices10.7. Classification of Semiconducting Memories10.8. Read and Write Memory10.8.1. Static RAM10.8.2. Dynamic RAM10.8.3. Comparison between SRAM and10.8.4. Commonly Used ICs for RAM10.9. Read only memory (ROM)10.10. Masked ROM10.10.1. Programmable Read Only Memory (PROM)10.10.2. Erasable Programmable Read Only Memory (EPROM)10.10.3. Electrical Erasable Programmable Read Only Memory (EEPROM)10.10.4. NVRAM10.11. Solved Examples10.12. Summary10.13. Exercises