Digital Systems Design Using Vhdl by Charles H. Roth, Jr.Digital Systems Design Using Vhdl by Charles H. Roth, Jr.

Digital Systems Design Using Vhdl

byCharles H. Roth, Jr., Lizy K. John

Hardcover | January 1, 2017

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Learn how to effectively use the industry-standard hardware description language, VHDL, as DIGITAL SYSTEMS DESIGN USING VHDL, 3E integrates VHDL into the digital design process. The book begins with a valuable review of basic logic design concepts before introducing the fundamentals of VHDL. The book concludes with detailed coverage of advanced VHDL topics.
Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. In addition to co-authoring DIGITAL SYSTEMS DESIGN USING VHDL, Dr. Roth has authored the successful FUNDAMENTALS OF LOGIC DESIGN and co-authored DIGITAL SYSTEMS DESIG...
Title:Digital Systems Design Using VhdlFormat:HardcoverDimensions:592 pages, 9.38 × 8.25 × 1.13 inPublished:January 1, 2017Publisher:Thomson-Engineering (NelsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:1305635140

ISBN - 13:9781305635142

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Table of Contents

1. REVIEW OF LOGIC DESIGN FUNDAMENTALS.Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing / Tristate Logic and Busses.2. INTRODUCTION TO VHDL.Computer-Aided Design. Hardware Description Languages. VHDL Description of Combinational Circuits. VHDL Modules. Sequential Statements and VHDL Processes. Modeling Flip-Flops Using VHDL Processes. Processes Using Wait Statements. Two Types of VHDL Delays: Transport and Inertial Delays. Compilation, Simulation, and Synthesis of VHDL Code. VHDL Data Types and Operators. Simple Synthesis Examples. VHDL Models for Multiplexers. VHDL Libraries. Modeling Registers and Counters Using VHDL Processes. Behavioral and Structural VHDL. Variables, Signals, and Constants. Arrays. Loops in VHDL. Assert and Report Statements.3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES.Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs).4. DESIGN EXAMPLES.BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers.5. SM CHARTS AND MICROPROGRAMMING.State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines.6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS.Implementing Functions in FPGAs. Implementing Functions Using Shannon's Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates Versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing.7. FLOATING-POINT ARITHMETIC.Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations.8. ADDITIONAL TOPICS IN VHDL.VHDL Functions. VHDL Procedures. Attributes. Creating Overloaded Operators. Multi-Valued Logic and Signal Resolution. The IEEE 9-Valued Logic System. SRAM Model Using IEEE 1164. Model for SRAM Read/Write System. Generics. Named Association. Generate Statements. Files and TEXTIO.9. DESIGN OF A RISC MICROPROCESSOR.The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model.10. HARDWARE TESTING AND DESIGN FOR TESTABILITY.Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundry Scan. Built-In Self-Test.11. ADDITIONAL DESIGN EXAMPLES.Design of a Wristwatch / Memory Timing Models. A Universal Asynchronous Receiver Transmitter (UART).Appendix A: VHDL Language Summary.Appendix B: IEEE Standard Libraries.Appendix C: TEXTIO Package.Appendix D: Projects.References.