Efficient Test Methodologies for High-Speed Serial Links by Dongwoo HongEfficient Test Methodologies for High-Speed Serial Links by Dongwoo Hong

Efficient Test Methodologies for High-Speed Serial Links

byDongwoo Hong, Kwang-Ting Cheng

Paperback | March 1, 2012

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Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.

Title:Efficient Test Methodologies for High-Speed Serial LinksFormat:PaperbackDimensions:98 pages, 23.5 × 15.5 × 0.07 inPublished:March 1, 2012Publisher:Springer-Verlag/Sci-Tech/TradeLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9400730942

ISBN - 13:9789400730946

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Table of Contents

Chapter 1 Intorduction. 1 Overview of High-Speed Serial Links. 1.1 High-Speed Serial Link System. 1.2 Testing High-Speed Serial Links. 2 Challenges in Testing High-Speed Serial Links. 3 Contributions of the Dissertation. Chapter 2 An Efficient Jitter Measurement Technique. 1 Comparator Undersampling Technique. 2 Random Jitter Measurement. 2.1 Proposed RJ Measurement Technique. 2.2 Limitations of the Technique. 3 Experimental Results. 3.1 Simulation Results. 3.2 Measurement Results. 4 Summary. Chapter 3 BER Estimation for Linear Clock and Data Recovery Circuit. 1 BER Analysis with Random Jitter. 1.1 Error Occurrences. 1.2 BER Estimation with Random Jitter. 2 BER Analysis with Random Jitter and Periodic Jitter. 2.1 Jitter Transfer Characteristics of a CDR Circuit. 2.2 BER Estimation with RJ and PJ. 3 BER Analysis Including Intrinsic Noise in the CDR Circuit. 4 Experimental Results. 4.1 Simulation Results. 4.2 Hardware Validation Results. 5 Summary and Future Work. Chapter 4 BER Estimation for Non-Linear Clock and Data Recovery Circuit. 1 Jitter Analysis for BB CDR Circuits. 1.1 Jitter Transfer Analysis. 1.2 Jitter Tolerance Analysis. 2 BER Estimation. 2.1 Variation of Jitter Transfer due to RJ. 2.2 BER Estimation. 3 Experimental Setup and Results. 3.1 Simulation Setup. 3.2 Simulation Results. 4 Summary. Chapter 5 Gaps in Timing Margining Test. 1 Timing Margining Test Basics. 2 Gap Analysis in Timing Margining Test. 2.1 Random Jitter. 2.2 PLL-Based Clock Recovery with Non-Linear Phase Detector. 2.3 Jitter Amplification. 2.4 Duty Cycle Distortion in Clock. 3 Summary and Future Work. Chapter 6 An Accurate Jitter Estimation Technique. 1 Characteristics of DJ. 1.1 ISI Induced Jitter. 1.2 Crosstalk Induced Jitter. 2 Total Jitter Estimation. 2.1 Estimation Based on Dual-Dirac Model. 2.2 High-Order Polynomial Fitting. 2.3 Accuracy vs. Number of Samples for Fitting. 3 Summary. Chapter 7 A Two-Tone Test Method for Continuous-Time Adaptive Equalizers. 1 Continous-Time Adaptive Equalizer. 2 Proposed Two-Tone Test Method. 2.1 Description of the Test Method. 2.2 Implementation of the Test Method. 3 Experimental Results. 3.1 MATLAB Simulation Results. 3.2 Transistor-Level Simulation Results. 4 Summary and Future Work. Chapter 8 Conclusions. Appendix A. References .