Electromigration Modeling at Circuit Layout Level by Cher Ming TanElectromigration Modeling at Circuit Layout Level by Cher Ming Tan

Electromigration Modeling at Circuit Layout Level

byCher Ming Tan

Paperback | May 4, 2013

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Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.
Title:Electromigration Modeling at Circuit Layout LevelFormat:PaperbackDimensions:103 pagesPublished:May 4, 2013Publisher:Springer-Verlag/Sci-Tech/TradeLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9814451207

ISBN - 13:9789814451208

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Table of Contents

CHAPTER 1 Introduction

1.1 Overview of Electromigration

1.2 Modeling of Electromigration

1.3 Organization of the Book

1.4 Summary

CHAPTER 2 3D Circuit Model Construction and Simulation

2.1 Introduction

2.2 Layout Extraction and 3D Model Construction

2.3 Transient Electro-thermo-structural Simulations and Atomic Flux Divergence (AFD) Computation

2.4 Simulation Results and Discussions

2.5 Effects of Barrier Thickness and Low-κ Dielectric on Circuit EM Reliability

2.6 Summary

CHAPTER 3 Comparison of EM Performances in Circuit and Test Structures

3.1 Introduction

3.2 Model Construction and Simulation Setup

3.3 Distributions of Atomic Flux Divergences under Different Operation Conditions

3.4 Effects of Interconnect Structures on Circuit EM Reliability

3.5 Effects of Transistor Finger Number on Circuit EM Reliability

3.6 Summary

CHAPTER 4 Interconnect EM Reliability Modeling at Circuit Layout Level

4.1 Introduction

4.2 Model Construction and Simulation Setup

4.3 Distributions of Atomic Flux Divergences

4.4 Effects of Layout and Process parameters on Circuit EM Reliability.

4.5 Summary

CHAPTER 5 Concluding Remarks

5.1 Conclusions

5.2 Recommenations for Future Work