Electronics System Design Techniques for Safety Critical Applications by Luca SterponeElectronics System Design Techniques for Safety Critical Applications by Luca Sterpone

Electronics System Design Techniques for Safety Critical Applications

byLuca Sterpone

Paperback | November 23, 2010

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The main purpose of the present manuscript addresses the development of techniques for the evaluation and the hardening of designs implemented on SRAM-based Field Programmable Gate Arrays against the radiation induced effects such as Single Event Upsets (SEUs) or Soft-Errors (SEs). The perspective of the analysis and the design flows proposed in this manuscript are aimed at defining a novel and complete design methodology solving the industrial designer's needs for implementing electronic systems using SRAM-based FPGAs in critical environments, like the space or avionic ones. The main contribution of the proposed manuscript consists in a new reliability-oriented place and route algorithm that, coupled with Triple Modular Redundancy (TMR), is able to effectively mitigate the effects of radiation in SRAM-based FPGA devices. The manuscript offers also the analysis of several fields where the usage of reconfigurable logic devices introduces several advantages such as the reconfigurable computing for multimedia applications and biomedical applications.
Winner of the EDAA (European Design Automation Association) Outstanding Monograph Award in the Reconfigurable Electronics section
Title:Electronics System Design Techniques for Safety Critical ApplicationsFormat:PaperbackDimensions:164 pages, 9.25 × 6.1 × 0.07 inPublished:November 23, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048180414

ISBN - 13:9789048180417

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Table of Contents

Preface.PART I 1. An Introduction to FPGA Devices in Radiation Environments. 2. Radiation Effects on SRAM-based FPGAs. 3. Analytical Algorithms for Faulty Effects Analysis. 4. Reliability-oriented Place and Route Algorithm. 5. A Novel Design Flow for Fault Tolerance.PART II 6. Configuration System Based on Internal FPGA Decompression. 7. Reconfigurable Devices for the Analysis of DNA Microarray. 8. Reconfigurable Compute Fabric Architectures.Index.