Hardware And Software: Verification And Testing: 10th International Haifa Verification Conference, Hvc 2014, Haifa, Israel by Eran YahavHardware And Software: Verification And Testing: 10th International Haifa Verification Conference, Hvc 2014, Haifa, Israel by Eran Yahav

Hardware And Software: Verification And Testing: 10th International Haifa Verification Conference…

byEran Yahav

Paperback | November 6, 2014

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This book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014. The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range of topics in the sub-fields of testing and verification applicable to software, hardware, and complex hybrid systems.
Title:Hardware And Software: Verification And Testing: 10th International Haifa Verification Conference…Format:PaperbackDimensions:302 pages, 23.5 × 15.5 × 0.17 inPublished:November 6, 2014Publisher:Springer-Verlag/Sci-Tech/TradeLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:3319133373

ISBN - 13:9783319133379

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Table of Contents

Using Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures.- Enhancing Scenario Quality Using Quasi-Events.- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems.- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification.- Generating Modulo-2 Linear Invariants for Hardware Model Checking.- Suraq - A Controller Synthesis Tool Using Uninterpreted Functions.- Synthesizing Finite-State Protocols from Scenarios and Requirements.- Automatic Error Localization for Software Using Deductive Verification.- Generating JML Specifications from Alloy Expressions.- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems.- Handling TSO in Mechanized Linearizability Proofs.- Partial Quantifier Elimination.- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study.- A Framework to Synergize Partial Order Reduction with State Interpolation.- Reduction of Resolution Refutations and Interpolants via Subsumption.- Read, Write and Copy Dependencies for Symbolic Model Checking.- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams.- Formal Verification of Secure User Mode Device Execution with DMA.- Supervisory Control of Discrete-Event Systems via IC3.- Partial-Order Reduction for Multi-core LTL Model Checking.- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution.