High-Speed Clock Network Design by Qing K. ZhuHigh-Speed Clock Network Design by Qing K. Zhu

High-Speed Clock Network Design

byQing K. Zhu

Hardcover | December 31, 2002

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High-Speed Clock Network Designis a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters as follows. Chapter 1 provides an overview to the design of clock networks. Chapter 2 specifies the timing requirements in digital design. Chapter 3 shows the circuits of sequential elements including latches and flip-flops. Chapter 4 describes the domino circuits, which need special clock signals. Chapter 5 discusses the phase-locked loop (PLL) and delay-locked loop (DLL), which provide the clock generation and de-skewing for the on-chip clock distribution. Chapter 6 summarizes the clock distribution techniques published in the state-of-the-art microprocessor chips. Chapter 7 describes the CAD flow on the clock network simulation. Chapter 8 gives the research work on low-voltage swing clock distribution. Chapter 9 explores the possibility of placing the global clock tree on the package layers. Chapter 10 shows the algorithms of balanced clock routing and wire sizing for the skew minimization. Chapter 11 shows a commercial CAD tool that deals with clock tree synthesis in the ASIC design flow. The glossary is attached at the end of this book. The clock network design is still a challenging task in most high-speed VLSI chips, since the clock frequency and power consumption requirements are increasingly difficult to meet for multiple clock networks on the chip. Many research works and industry examples will be shown in this area to continually improve the clock distribution networks for future high-performance chips.
Title:High-Speed Clock Network DesignFormat:HardcoverDimensions:188 pagesPublished:December 31, 2002Publisher:Kluwer Boston Inc.Language:English

The following ISBNs are associated with this title:

ISBN - 10:1402073461

ISBN - 13:9781402073465

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Table of Contents

Preface. 1: Introduction. 1.1. Clock frequency and power consumption. 1.2. Sources of clock skew and clock jitter. 1.3. On-die variations and clock skew impacts. 1.4. Clock buffer circuit design. 1.5. Power supply and reliability issues. 1.6. Design complexity of clock distribution. 1.7. Summary. 2: Overview to Timing Constraints. 2.1. Propagation delay and transition time. 2.2. Setup time constraint. 2.3. Hold time constraint. 2.4. Recovery time and pulse width. 2.5. Time borrowing. 2.6. One example: fixing holding time violations. 2.7. Delay slack graph for timing constraints. 2.8. Summary. 3: Sequential Clocked Elements. 3.1. Latch clocking. 3.2. Flip-flop clocking. 3.3. Power reduction. 3.4. Summary. 4: Design Methodology for Domino Circuits. 4.1. Domino circuit types. 4.2. Clock distribution for domino circuits. 4.3. Design optimization in domino circuits. 4.4. Low Vt devices for domino circuits. 4.5. Summary. 5: Clock Generation and De-skewing. 5.1. On-chip clock generation. 5.2. Characterization of clock generator. 5.3. Layout guidelines. 5.4. De-skewing circuits. 5.5. Clock shrinking technique for silicon debug. 5.6. Summary. 6: Microprocessor Clock Distribution Examples. 6.1. Intel IA-64. 6.2. Intel Pentium IV. 6.3. Intel Pentium III. 6.4. DEC Alpha. 6.5. IBM Power PC. 6.6. Summary. 7: Clock Network Simulation Methods. 7.1. RC extraction. 7.2. Full-chip clock tree racing. 7.3. Click tree simulation and report files. 7.4. IR drop effects. 7.5. Summary. 8: Low-Voltage Swing Clock Distribution. 8.1. 1/2Vdd swing local clock distribution. 8.2. Low voltage swing global clock distribution. 8.3. Summary. 9: Routing Clock on Package. 9.1. Scheme overview. 9.2. ESD design. 9.3. Transmission line noise on package. 9.4. Microprocessor experimental results. 9.5. Summary. 10: Balanced Clock Routing Algorithms. 10.1. Planar equal path length clock routing. 10.2. Geometrical embedding. 10.3. Skew-bounded refinement. 10.4. Wire sizing of clock network. 10.5. Summary. 11: Clock Tree Design Flow in ASIC. 11.1 Flow overview. 11.2. Gated clock tree synthesis. 11.3. Clock skew and topology reports. 11.4. Route the clock net. 11.5. Verify the clock skew. 11.6. Summary. Glossary. References. Index.