IQ Calibration Techniques for CMOS Radio Transceivers by Sao-Jie ChenIQ Calibration Techniques for CMOS Radio Transceivers by Sao-Jie Chen

IQ Calibration Techniques for CMOS Radio Transceivers

bySao-Jie Chen, Yong-Hsiang Hsieh

Paperback | November 30, 2010

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The 802.11n wireless standard uses 64-state quadrature amplitude modulation (64-QAM) to achieve higher spectral efficiency. Consequently, the transmitter and receiver require a higher signal to noise ratio with the same level of error rate performance. This book offers a fully-analog compensation technique without baseband circuitry to control the calibration process. Using an 802.11g transceiver design as an example, it describes in detail an auto-calibration mechanism for I/Q gains and phases imbalance.

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Title:IQ Calibration Techniques for CMOS Radio TransceiversFormat:PaperbackDimensions:109 pages, 9.45 × 6.3 × 0.03 inPublished:November 30, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048172799

ISBN - 13:9789048172795

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Table of Contents

List of Figures. List of Tables. List of Abbreviations. Preface. Acknowledgments.1. INTRODUCTION. 1. Wireless LAN Standards. 1.1 IEEE 802.11. 1.2 HiperLan. 1.3 HiperLan II. 1.4 OpenAir. 1.5 HomeRF and SWAP. 1.6 BlueTooth. 2. Wireless in the 21st Century. 3. The 802 Standard and The IEEE. 3.1 IEEE 802.11b. 3.2 IEEE 802.11a. 3.3 IEEE 802.11g. 3.4 Performance and Characeristic. 4. Background and Motivation. 5. IEEE 802.11g RF Transceiver Performance Requirement. 5.1 Synthesizer Output Phase Noise. 5.2 Circuit Linearity. 5.3 Modulator/Demodulator I/Q Gain and Phase Imbalance. 6 Transceiver Design Goal. 6.1 Solutions on I/Q Balance. 2. TRANSCEIVER ARCHITECTURE DESIGN. 1. Receiver Architecture. 1.1 Superheterodyne Receiver. 1.2 Low-IF Receiver. 1.3 Zero-IF Receiver. 2. Comparison of Our Choice. 3. Transceiver Architecture. 4. The Choice of Intermediary Frequency. 5. Receiver Chain Link Budget. 5.1 Receiver Adjacent Channel Rejection. 5.2 Receiver Cascade Gain. 5.3 Receiver Cascade Noise Figure. 5.4 Receiver Dynamic Range. 5.4.1 RF/IF Section Gain Windows. 5.4.2 Receiver IF VGA and I/Q Demodulator Specification. 5.4.3 Cascade Gain of IF/BB. 5.4.4 Cascade Noise Figure of IF/BB. 6. Transmitter Chain Link Budget. 6.1 Transmit Circuits Gain Distribution and Gain Range. 6.2 Transmit Error Vector Magnitude. 6.3 Transmit Signal Spectral Mask.3. I/Q MODULATOR AND DEMODULATOR DESIGN. 1. I/Q Modulator and Demodulator Architecture Overview. 2. Variable Gain Amplifier and Low-Pass Filter Re-use. 2.1 RX/TX Two-Mode Variable Gain Control Amplifier. 2.2 RX/TX Two-Mode Low-Pass Filter. 2.3 DC Offset Cancellation.4. AN AUTO-I/Q CALIBRATED MODULATOR. 1. DC Offset, I/Q Gain and Phase Imbalance. 2. DC Offset, I/Q Gain and Phase Imbalance Auto-Calibration. 2.1 DC Offset Auto-Calibration. 2.2 I/Q Gain Imbalance Auto-Calibration. 2.3 I/Q Quadrature Phase Mismatch Auto-Calibration. 2.4 Implementation of I/Q Auto-Calibration Circuitry. 2.5 TX I/Q Auto-Calibration Measurement Result. 5. AN AUTO-I/Q CALIBRATED DEMODULATOR. 1. Single Test Tone Design. 2. I/Q Gain Imbalance and Quadrature Phase Mismatch Auto-Calibration. 2.1 I/Q Gain Imbalance Auto-Calibration. 2.2 I/Q Quadrature Phase Mismatch Auto-Calibration. 2.3 Implementation of I/Q Auto-Calibration Circuitry. 3. RX I/Q Auto-Calibration Measurement Result. 6. SYSTEM MEASUREMENT RESULT. 1. Transmitter Measurement Result. 2. Receiver Measurement Result. 7. CONCLUSION.References.