Low-Power Design of Nanometer FPGAs: Architecture and EDA by Mohab HassanLow-Power Design of Nanometer FPGAs: Architecture and EDA by Mohab Hassan

Low-Power Design of Nanometer FPGAs: Architecture and EDA

byMohab Hassan, Mohab AnisEditorHassan

Hardcover | September 28, 2009

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Low-Power Design of Nanometer FPGAs Architecture and EDAis an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.

  • Low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign
  • Comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation
  • Provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques
Hassan Hassan is currently a staff engineer in the timing and power group at Actel Corporation. He has authored/coauthored more than 20 papers in international journals and conferences. His research interests include integrated circuit design and design automation for deep submicron VLSI systems. He is also a member of the program comm...
Title:Low-Power Design of Nanometer FPGAs: Architecture and EDAFormat:HardcoverDimensions:256 pages, 9.25 × 7.5 × 0.98 inPublished:September 28, 2009Publisher:Morgan KaufmannLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0123744385

ISBN - 13:9780123744388


Table of Contents

Chapter 1: FPGA Overview: Architecture and CAD Chapter 2: Power Dissipation in Modern FPGAs Chapter 3: Power Estimation in FPGAs Chapter 4: Dynamic Power Reduction Techniques in FPGAs Chapter 5: Leakage Power Reduction in FPGAs Using MTCMOS Techniques Chapter 6: Leakage Power Reduction in FPGAs Through Input Pin Reordering