Low-Power High-Speed ADCs for Nanometer CMOS Integration by Zhiheng CaoLow-Power High-Speed ADCs for Nanometer CMOS Integration by Zhiheng Cao

Low-Power High-Speed ADCs for Nanometer CMOS Integration

byZhiheng Cao, Shouli Yan

Paperback | November 22, 2010

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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Title:Low-Power High-Speed ADCs for Nanometer CMOS IntegrationFormat:PaperbackDimensions:108 pages, 9.25 × 6.1 × 0.03 inPublished:November 22, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048178851

ISBN - 13:9789048178858

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Table of Contents

Preface. List of Tables. List of Figures.  1. Introduction. 1 Motivations. 2 A Review of Existing ADC Architectures.2. A 52mW 10b 210MS/s Two-Step ADC for Digital IF Receivers in 130nm CMOS. 1 Background. 2 Architecture and Circuits. 3 Experimental Results. 4 Summary.3. A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 130nm Digital CMOS 47. 1 Background. 2 Architecture. 3 Enabling Circuits. 4 Testing Issues. 5 Experimental Results. 6 Performance Summary and Comparison. 7 Summary.4. A 0.4ps-RMS-Jitter 1-3GHz Clock Multiplier PLL Using Phase-Noise Preamplification. 1 Introduction. 2 Phase-Lock Loop (PLL). 3 VCO and Clock Buffers. 4 Experimental Results. 5 Summary.5. Conclusions and Future Directions. References. About the Authors.