Multi-Microprocessor Systems for Real-Time Applications by Gianni ConteMulti-Microprocessor Systems for Real-Time Applications by Gianni Conte

Multi-Microprocessor Systems for Real-Time Applications

EditorGianni Conte, Dante del Corso

Paperback | October 19, 2011

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The continous development of computer technology supported by the VLSI revolution stimulated the research in the field ·of multiprocessors systems. The main motivation for the migration of design efforts from conventional architectures towards multiprocessor ones is the possibi I ity to obtain a significant processing power together with the improvement of price/performance, reliability and flexibility figures. Currently, such systems are moving from research laboratories to real field appl ications. Future technological advances and new generations of components are I ikely to further enhance this trend. This book is intended to provide basic concepts and design methodologies for engineers and researchers involved in the development of mul tiprocessor systems and/or of appl ications based on multiprocessor architectures. In addition the book can be a source of material for computer architecture courses at graduate level. A preliminary knowledge of computer architecture and logical design has been assumed in wri ting this book. Not all the problems related with the development of multiprocessor systems are addressed in th i s book. The covered range spans from the electrical and logical design problems, to architectural issues, to design methodologis for system software. Subj ects such as software development in a multiprocessor environment or loosely coupled multiprocessor systems are out of the scope of the book. Since the basic elements, processors and memories, are now available as standard integrated circuits, the key design problem is how to put them together in an efficient and reliable way.
Title:Multi-Microprocessor Systems for Real-Time ApplicationsFormat:PaperbackPublished:October 19, 2011Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9401088888

ISBN - 13:9789401088886

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Table of Contents

1. Multiprocessor System Architecture.- 1.1 Distributed Processing and Multiprocessors.- 1.1.1 Classification Criteria.- 1.1.2 Computer Networks.- 1.1.3 Multiple Processor Systems.- 1.1.4 Special Purpose Machines.- 1.1.5 Other Classifications of Distributed Systems.- 1.2 Multiprocessor Systems.- 1.2.1 Multiprocessor Structures.- 1.2.2 The Interconnection Network.- 1.2.3 Shared Bus.- 1.2.4 Multiport Memory.- 1.2.5 Crossbar Switches.- 1.2.6 Multistage Interconnection Networks.- 1.2.7 Applications of Multiple Processors.- 1.3 Description Techniques for Multiprocessors.- 1.3.1 Levels of Description.- 1.3.2 Selection of the Description Level.- 1.3.3 The PMS Notation.- 1.3.4 The MSBI Notation.- 1.4 Some Multiprocessor Systems.- 1.4.1 Selection Criteria.- 1.4.2 The Cm*.- 1.4.3 The C.mmp.- 1.4.4 The PLURIBUS.- 1.4.5 The ?* System.- 1.4.6 The iAPX432 System.- 1.4.7 The TOMP Multiprocessor System.- 1.5 References.- 2. Performance Analysis of Multiprocessor Systems.- 2.1 Performance Evaluation of Bus Oriented Multiprocessor Systems.- 2.1.1 Introduction.- 2.1.2 Modeling Assumptions.- 2.1.3 The System Workload.- 2.1.4 Architecture 1.- 2.1.5 Architecture 2.- 2.1.6 Architecture 3.- 2.1.7 Architecture 4.- 2.1.8 Architecture Comparison.- 2.1.9 Choice of the Architecure of TOMP.- 2.2 Other Modeling Techniques and Measurements.- 2.2.1 Introduction.- 2.2.2 Stochastic Petri Net Models.- 2.2.3 Queueing Network Models.- 2.2.4 Measurements.- 2.3 References.- 3. TOMP Software.- 3.1 Introduction.- 3.1.1 Goals and Motivations.- 3.1.2 Limits.- 3.1.3 Overall System Description.- 3.2 Interprocess Communication.- 3.2.1 Model and Primitive Operations.- 3.2.2 Low Level Communication Protocol.- 3.3 The Executive.- 3.3.1 System Initialization.- 3.3.2 Process Management.- 3.3.3 Interrupt Handling.- 3.3.4 Monitoring Functions.- 3.4 Monitoring and Debug.- 3.4.1 General Architecture.- 3.4.2 Debugging Functions.- 3.5 Utilities.- 3.5.1 Terminal Handler.- 3.5.2 File System.- 3.5.3 Common Memory Allocator.- 3.6 System Generation.- 3.7 A Critical Review.- 3.8 References.- 4. Design of Multiprocessor Buses.- 4.1 Introduction.- 4.2 Basic Protocols.- 4.2.1 Elementary Operations.- 4.2.2 Types of Information Transfer Cycles.- 4.2.3 Synchronization of the Action Flow.- 4.3 Bused Systems.- 4.3.1 Channel Allocation Techniques.- 4.3.2 Bus Arbitration.- 4.3.3 The Distributed Self-selection Arbiter.- 4.4 Electrical Behaviour of Backplane Lines.- 4.4.1 Definition of Signal Levels.- 4.4.2 Transmission Line Effects.- 4.4.3 Crosstalk.- 4.4.4 Protocol Speed.- 4.5 Protocol Extension.- 4.5.1 The Enable/Disable Technique.- 4.5.2 Bus Supervisors.- 4.6 References.- 5. Some Examples of Multiprocessor Buses.- 5.1 Introduction.- 5.2 The Multibus Backplane.- 5.2.1 History and Main Features.- 5.2.2 Physical and Electrical Specifications.- 5.2.3 The Information Transfer Protocol.- 5.2.4 Special Features.- 5.2.5 Timing and Pinout.- 5.3 The VME Backplane Bus.- 5.3.1 History and Main Features.- 5.3.2 Physical and Electrical Specifications.- 5.3.3 The Information Transfer Protocol.- 5.3.4 Special Features.- 5.4 The 896 Backplane Bus.- 5.4.1 History and Main Features.- 5.4.2 Physical and Electrical Specifications.- 5.4.3 The Information Transfer Protocol.- 5.4.4 Special Features.- 5.4.5 Timing and Pinout.- 5.5 The M3BUS Backplane.- 5.5.1 History and Main Features.- 5.5.2 Physical and Electrical Specifications.- 5.5.3 System Organization and Control.- 5.5.4 The Arbitration Protocol.- 5.5.5 The Addressing Protocol.- 5.5.6 The Data Transfer Protocol.- 5.5.7 Interrupt and Interprocessor Communication.- 5.5.8 Supervisor Protocol.- 5.5.9 The Serial Bus.- 5.5.10 Timing and Pinout.- 5.6 References.- 6. Hardware Modules for Multiprocessor Systems.- 6.1 Introduction.- 6.2 System Design.- 6.2.1 Physical Organization of Multiprocessor Systems.- 6.2.2 Board Design Guidelines.- 6.3 Slave Modules.- 6.3.1 Organization of Slave Modules.- 6.3.2 Address Decoders and Latches.- 6.3.3 Slave Control Logic.- 6.3.4 Slave Buffering.- 6.4 Master Modules.- 6.4.1 Organization of Master Modules.- 6.4.2 External Access Decoder and Bus Arbitration.- 6.4.3 Master Control Logic.- 6.4.4 Master Buffering.- 6.5 Interrupt Structures.- 6.5.1 Requirements for Multiprocessor Systems.- 6.5.2 System Controls.- 6.5.3 Processor Interrupts.- 6.5.4 Centralized Interrupt Handler.- 6.5.5 Distributed Interrupt Handler.- 6.5.6 Serial Lines.- 6.6 Special Modules.- 6.6.1 Multiple-slave Modules.- 6.6.2 Bus Windows.- 6.6.3 Dual-port Slaves.- 6.6.4 Master-slave Modules.- 6.6.5 Block Transfer Units.- 6.6.6 Supervisor Modules.- 6.7 References.- 7. Multiprocessor Benchmarks.- 7.1 Introduction.- 7.2 The Concept of Performance.- 7.3 Parallel Programming.- 7.4 Parallel Notation Form.- 7.5 Parallel Sorting Techniques.- 7.6 Measurements and Analysis of Results.- 7.7 Conclusion.- 7.8 References.