Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs by Pedro M. FigueiredoOffset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs by Pedro M. Figueiredo

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and…

byPedro M. Figueiredo

Paperback | October 28, 2010

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Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Pedro Figueiredo received the degrees of Licenciado and Doutor (PhD) in Electrical and Computer Engineering in 1999 and 2006, respectively, from the Instituto Superior Técnico (IST), Lisbon, Portugal. From 1997 to 1999, he was with the Analog and Mixed-Mode Circuits Group in the Institute for Systems and Computer Engineering (INESC), L...
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Title:Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and…Format:PaperbackDimensions:404 pages, 9.25 × 6.1 × 0.01 inPublished:October 28, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048181925

ISBN - 13:9789048181926

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Table of Contents

Preface. List of Symbols and Abbreviations.1 High-Speed ADC Architectures. 1.1 Introduction. 1.2 The Analog-to-Digital Converter. 1.3 Flash ADCs. 1.4 Two-Step Flash ADCs. 1.5 Folding and Interpolation ADCs. 1.6 Building Blocks of CMOS High-Speed ADCs.2 Averaging Technique - DC Analysis and Termination. 2.1 Introduction. 2.2 Published Studies on the Averaging Technique. 2.3 Output Voltage and Gain. 2.4 Effect of Mismatches - INL and DNL. 2.5 Averaging in Folding Circuits. 2.6 Considerations About the Yield. 2.7 Termination of the Averaging Network. 3 Averaging Technique - Transient Analysis and Automated Design. 3.1 Introduction. 3.2 Flash ADC Architecture. 3.3 Output Voltage and Gain. 3.4 Effect of Mismatches. 3.5 Design of Averaged Pre-Amplifier Stages in Flash ADCs.4 Integrated Prototypes using Averaging. 4.1 Introduction. 4.2 7-bit 120 MS/s I/Q flash ADC. 4.3 10-bit 100 MS/s Folding and Interpolation ADC.5 Offset Cancellation Methods. 5.1 Introduction. 5.2 Offset Cancellation Techniques. 5.3 New Offset Cancellation Technique. 5.4 6-bit 1 GHz Two-Step Subranging ADC.6 Conclusions. 6.1 Overview of the Research Work.Appendix A Averaging with Piecewise Linear Differential Pairs. A.1 Introduction. A.2 Output Voltage and Gain. A.3 Effect of Mismatches - INL and DNL.Appendix B Mismatches in the Resistors of the Aveaging Network. B.1 Introduction. B.2 Mismatches in Resistors R0. B.3 Mismatches in Resistors R1.Appendix C Averaging in Folding Stages. C.1 Introduction. C.2 Equivalence Between Circular and Infinite Networks. C.3 Output Voltage and Gain. C.4 Effect of Mismatches.References. Index.