Quality-Driven SystemC Design by Daniel GroßeQuality-Driven SystemC Design by Daniel Große

Quality-Driven SystemC Design

byDaniel Große, Rolf Drechsler

Paperback | October 16, 2014

Pricing and Purchase Info

$155.76 online 
$168.95 list price save 7%
Earn 779 plum® points

Prices and offers may vary in store


In stock online

Ships free on orders over $25

Not available in stores


A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

Title:Quality-Driven SystemC DesignFormat:PaperbackPublished:October 16, 2014Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9400791925

ISBN - 13:9789400791923

Look for similar items by category:


Table of Contents

Dedication. List of Figures. List of Tables. Preface. Acknowledgments. 1. INTRODUCTION. 2. PRELIMINARIES. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 SystemC. 3. SYSTEM-LEVEL VERIFICATION. 3.1 Constraint-based Simulation. 3.2 Improvements for Constraint-based Simulation. 3.3 Contradiction Analysis for Constraint-based Simulation. 3.4 Measuring the Quality of Testbenches. 3.5 Summary and Future Work. 4. BLOCK-LEVEL VERIFICATION. 4.1 Property Checking. 4.2 Acceleration of Iterative Property Checking. 4.3 Contradictory Antecedent Debugging for Property Checking. 4.4 Analyzing Functional Coverage in Property Checking. 4.5 Summary and Future Work. 5. TOP-LEVEL VERIFICATION. 5.1 Checker Generation. 5.2 HW/SW Co-Verification for Embedded Systems. 5.3 Summary and Future Work. 6. SUMMARY AND CONCLUSIONS. References. Index.