Resource Efficient Ldpc Decoders: From Algorithms To Hardware Architectures by Sayed Mahfuzul Aziz

Resource Efficient Ldpc Decoders: From Algorithms To Hardware Architectures

bySayed Mahfuzul Aziz, Vikram A. Chandrasetty

Paperback | October 1, 2017

not yet rated|write a review

Pricing and Purchase Info

$189.50

Earn 948 plum® points

Pre-order online

Ships free on orders over $25

Not yet available in stores

about

Resource Efficient LDPC Decoders: From Algorithms to Hardware Architecturestakes a practical hands-on approach to developing low complexity algorithms and how to transform them into working hardware. It follows a complete design approach, from algorithms to hardware architectures , and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. Readers will learn modern techniques to design, model and analyze low complexity LDPC algorithms, along with tactics on their hardware implementation, how to reduce computational complexity and power consumption using computer-aided design techniques, and all aspects of the design spectrum, from algorithms to hardware implementation and performance tradeoffs.



  • Provides extensive treatment of LDPC decoding algorithms and hardware implementations
  • Presents systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms
  • Addresses some of the challenges associated with design, providing insight into implementing innovative architectures

About The Author

Syed Mahfuzul Aziz has over 31 years of experience in research & development, university teaching and industry engagement. Currently a professor of Electrical & Electronic Engineering at the University of South Australia, he has been involved in many industry projects and won competitive government and industry grants. In 1996, he was ...

Details & Specs

Title:Resource Efficient Ldpc Decoders: From Algorithms To Hardware ArchitecturesFormat:PaperbackDimensions:475 pages, 9.41 × 7.24 × 0.98 inPublished:October 1, 2017Publisher:Academic PressLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0128112557

ISBN - 13:9780128112557

Customer Reviews of Resource Efficient Ldpc Decoders: From Algorithms To Hardware Architectures

Reviews

Extra Content

Table of Contents

1. Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. Hardware architectures for LDPC codes 6. Prototyping LDPC codes in the hardware 7. Applications of resource efficient LDPC decoders Appendix-I: C-Programs and MATLAB models for simulating the performance of LDPC encoding/decoding algorithms Appendix-II: HDL codes for FPGA/ASIC implementation of selected LDPC encoder/decoder architectures