Robust Computing with Nano-scale Devices: Progresses and Challenges by Chao HuangRobust Computing with Nano-scale Devices: Progresses and Challenges by Chao Huang

Robust Computing with Nano-scale Devices: Progresses and Challenges

byChao Huang

Paperback | May 5, 2012

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Robust Nano-Computing focuses on various issues of robust nano-computing, defect-tolerance design for nano-technology at different design abstraction levels. It addresses both redundancy- and configuration-based methods as well as fault detecting techniques through the development of accurate computation models and tools. The contents present an insightful view of the ongoing researches on nano-electronic devices, circuits, architectures, and design methods, as well as provide promising directions for future research.

Title:Robust Computing with Nano-scale Devices: Progresses and ChallengesFormat:PaperbackDimensions:180 pages, 23.5 × 15.5 × 0.01 inPublished:May 5, 2012Publisher:Springer-Verlag/Sci-Tech/TradeLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9400731833

ISBN - 13:9789400731837

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Table of Contents

Chapter 1: Introduction. Chapter 2: Fault Tolerant Nano-Computing; Bharat Joshi, Dhiraj K. Pradhan, and Saraju P. Mohanty. 2.1 Introduction. 2.2 Principles of Fault Tolerant Nano-Computer Systems. 2.3 Process Variations in Nano-scale Circuits. 2.4 Fault Tolerant Nano-Computer Applications. 2.5 Trends and Future. Chapter 3: Transistor-Level Based Defect-Tolerance for Reliable Nano-Electronics; Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, and Ahmad Al-Yamani. 3.1 Introduction. 3.2 Previous Approaches. 3.3 Proposed Defect Tolerance Technique. 3.4 Experimental Results. 3.5 Conclusion. Chapter 4: Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays; Yexin Zheng and Chao Huang. 4.1 Introduction. 4.2 Background. 4.3 Redundancy-Based Defect-Tolerant Techniques. 4.4 Defect-Aware Logic Mapping for Nanowire-Based PLA. 4.5 Experimental Results. 4.6 Conclusions and Perspectives. Chapter 5: Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics; Mohammad Tehranipoor. 5.1 Introduction. 5.2 Related Prior Work. 5.3 BIST Procedure. 5.4 Test Configurations. 5.5 Recovery Analysis. 5.6 Simulation and Results. 5.7 Discussion. 5.8 Conclusion. Chapter 6: The Prospect and Challenges of CNFET-Based Circuits - A Physical Insight; Bipul C. Paul; 6.1 Introduction. 6.2 Fundamentals of CNFET. 6.3 Compact Model of CNFET. 6.4 Impact of Parasitics on Circuit Performance. 6.5 Impact of Process Variation. 6.6 Summary. 6.7 Appendix. Chapter 7: Computing with Nanowires - A Self Assembled Neuromorphic Architecture; S. Bandyopadhyay, K. Karahaliloglu, and S. Patibandla. 7.1 Introduction. 7.2 Self Assembly of Neuromorphic Networks. 7.3 Electrical Characterization of the Nanowires. 7.4 Simulation Results. 7.5 Conclusion. Chapter 8: Computational Opportunities and CADfor Nanotechnologies; M. Nicolaidis and E. Kolonis. 8.1 Introduction. 8.2 A Holistic CAD Platform for Nanotechnologies. 8.3 High-Level Modeling and Simulation Tool. 8.4 Artificial Ecosystems. 8.5 Systems of Particles and Emergence of Relativistic Space-Time. 8.6 Nano-Network Architecture Fit Tool. 8.7 Circuit Synthesis Tool. 8.8 Architectures for Complex Systems Implementation. 8.9 Non-Conventional Architectures. 8.10 Conclusions. Index.