SOI Circuit Design Concepts by Kerry Bernstein

SOI Circuit Design Concepts

byKerry Bernstein, Norman J. Rohrer

Paperback | September 18, 2007

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This book first introduces SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms, which are observed in common high-speed microprocessor designs. The book also offers rules of thumb and comparisons to conventional bulk CMOS to guide implementation and describes a number of unique circuit topologies that SOI supports.

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Title:SOI Circuit Design ConceptsFormat:PaperbackDimensions:239 pages, 9.25 × 6.1 × 0.03 inPublished:September 18, 2007Publisher:Springer USLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0387740996

ISBN - 13:9780387740997

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Table of Contents

Preface. 1: The Time for SOI. 1.1. Technology Scaling in VLSI. 1.2. The End of Moore's Law? 1.3. The Case for PD-SOI. 1.4. Summary. 2: SOI Device Structures. 2.1. Introduction. 2.2. Wafer Fabrication. 2.3. Patterning SOI Regions. 2.4. Transistor Structures. 2.5. Diodes. 2.6. Resistors. 2.7. Decoupling Capacitors. 2.8. Summary. 3: SOI Device Electrical Properties. 3.1. Introduction. 3.2. SOI MOSFET's Junction Diode. 3.3. Impact Ionization. 3.4. Floating Body Effects. 3.5. SOI MOSFET Modeling. 3.6. Insulator-Related Effects. 3.7. Composite Responses. 3.8. Summary. 4: Static Circuit Design Response. 4.1. Introduction. 4.2. Parameters of Interest to Circuit Designers. 4.3. First Switch vs. Second Switch. 4.4. First Switch vs. Steady State. 4.5. Static Circuit Response to SOI. 4.6. Passgate Circuit Response. 4.7. Summary. 5: Dynamic Circuit Design Considerations. 5.1. Introduction. 5.2. Dynamic Circuit Response. 5.3. Preferred Dynamic Design Practices. 5.4. Keeping Dynamic SOI Problems in Perspective. 5.5. Soft Errors in Dynamic Logic. 5.6. Dynamic Logic Performance. 5.7. Conclusions. 6: SRAM Cache Design Considerations. 6.1. Overview. 6.2. Writing a Cell. 6.3. Reading a Cell. 6.4. Cell Stability and Cell Bias. 6.5. SRAM Noise Considerations. 6.6. Precharging Circuitry. 6.7. Soft Error Upsets. 6.8. Array Test in PD-SOI. 6.9. Summary. 7: Specialized Function Circuits in SOI. 7.1. Introduction. 7.2. Timing Elements. 7.3. Latch Response in SOI. 7.4. Input/Output Circuitry. 7.5. Electro-Static Discharge (ESD) Protection. 7.6. Summary. 8: Global Chip Design Considerations. 8.1. Introduction. 8.2. Temperature Effects. 8.3. Noise Immunity. 8.4. Power Consumption. 8.5. Power Supply Issues Noise. 8.6. System Performance. 8.7. SOI Timing Variability. 8.8. Summary. 9: Future Opportunities in SOI. 9.1. Introduction. 9.2. Floating body Effect Suppression. 9.3. DTCMOS. 9.4. DGCMOS. 9.5. 3-Dimensional SOI. 9.6. Future Scaling Opportunities. 9.7. Summary. About the Authors. Index.