Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms by Zhe MaSystematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms by Zhe Ma

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based…

byZhe Ma, Pol Marchal, Daniele Paolo Scarpazza

Paperback | October 19, 2010

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Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platforms gives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications.Many of these applications are concurrent in the sense that multiple subsystems can be running simultaneously. Also, these applications are so dynamic at run-time that the designs based on the worst case execution times are inefficient in terms of resource allocation (e.g., energy budgets). A novel systematical approach is clearly necessary in the area of system-level design for the embedded systems where those concurrent and dynamic applications are mapped. This material is mainly based on research at IMEC and its international university network partners in this area in the period 1997-2006. In order to deal with the concurrent and dynamic behaviors in an energy-performance optimal way, we have adopted a hierarchical system model (i.e., the gray-box model) that can both exhibit the sufficient detail of the applications for design-time analysis and hide unnecessary detail for a low-overhead run-time management. We have also developed a well-balanced design-time/run-time combined task scheduling methodology to explore the trade-off space at design-time and efficiently handle the system adaptations at run-time. Moreover, we have identified the connection between task-level memory/communication management and task scheduling and illustrated how to perform the task-level memory/communication management in order to obtain the design constraints that enable the this connection. A fast approach is also shown to estimate at the system-level, the energy and performance characterization of applications executing on the target platform processors.

About The Author

Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer.

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Title:Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based…Format:PaperbackDimensions:276 pagesPublished:October 19, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048176107

ISBN - 13:9789048176106

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Table of Contents

Chapter 1: Introduction. 1.1 The System-on-Chip Era. 1.2 Characteristics of Embedded Software. 1.3 Context and Motivation. 1.4 TCM Framework. 1.5 Overview of Chapters. Chapter 2: Related Work. 2.1 Real-time Scheduling. 2.2 Low-power Considerations. 2.3 Platform Issues and Co-design Framework.Chapter 3: System Model and Work flow. 3.1 Overview of TCM Work flow. 3.2 Gray-box Model. 3.3 System Scenario Selection. 3.4 Two-phase Scheduling. 3.5 Summary.Chapter 4: Basic Design-time Scheduling. 4.1 Problem Formulation. 4.2 Exact Scheduling Algorithms. 4.3 Forward Search Algorithm. 4.4 Backward Search Algorithm. 4.5 Sub-platform Scheduling. 4.6 Handling Timing-Constraints. 4.7 Summary.Chapter 5: Scalable Design-time Scheduling. 5.1 Introduction. 5.2 Motivational Example. 5.3 Thread Frame Decomposition. 5.4 Thread Partition Clustering. 5.5 Thread Partition Interleaving. 5.6 Experimental Results and Discussions. 5.7 Comparison with State of the Art. 5.8 Summary.Chapter 6: Fast and Scalable Run-time Scheduling. 6.1 Two-Phase Task Scheduling: Why and How. 6.2 Run-time Scheduling Algorithm. 6.3 Experimental Results. 6.4 Summary. Chapter 7: Handling of Multi-dimensional Pareto Curves. 7.1 Overview of The Customized Run-time Management. 7.2 Problem Formulation of Run-time Operating Point Selector. 7.3 Related Work. 7.4 MP-SoC Heuristic Description. 7.5 Experimental Results. 7.6 Summary. Chapter 8: Run-time Software Multithreading. 8.1 Motivation of Run-time Re-scheduling. 8.2 Run-time Interleaving. 8.3 Experimental Results and Discussion. 8.4 Comparison with State of the Art. 8.5 Summary.Chapter 9: Fast Source-level Performance Estimation. 9.1 Introduction. 9.2 Motivational Example. 9.3 Comparison With State of The Art. 9.4 Fundamentals of The Estimation Technique. 9.5 Experimental Results. 9.6 Summary.Chapter 10: Handling of Task-level Data Communication and Storage. 10.1 Memory Architecture. 10.2 Exploring Thread Node Level Data Reuse. 10.3 Data Assignment On L1 Memory Layer. 10.4 Bandwidth Aware Scheduling. 10.5 Handling inter-TN and inter-TF Data Transfers. 10.6 Summary.Chapter 11: Demonstration on Heterogeneous Multiprocessor SoCs. 11.1 Motivation for Heterogeneous Multiprocessor Platforms. 11.2 Mapping Visual Texture Coding Decoder. 11.3 Summary.Chapter 12: Conclusions and future research work. Input and output data of scheduling examples in Section 4.3.1. References.