The Art of Analog Layout by Alan HastingsThe Art of Analog Layout by Alan Hastings

The Art of Analog Layout

byAlan Hastings

Paperback | June 24, 2005

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Verbal explanations are favored over mathematical formulas, graphs are kept to a minimum, and line drawings are used in this user-friendly book. Clear guidance and advice are provided for those professionals who lay out analog circuits. Matching of resistors and capacitors: Includes causes of mismatch, particularly the hydrogen effect and package shift. MOS Transistors: Covers a brief history of floating gate devices, EPROM and EEPROM. Applications of MOS transistors: Expands information on failure mechanisms, including BVdss/Bvdii, SILC, NBTI/PTBI and GIDL and the difference between electrical and electrothermal SOA. Consideration of failure mechanisms as crucial to layout: Integrates further information into many chapters covering various devices. Standard bipolar, polygate CMOS and analog BiCMOS: Covers all three fundamental processes. A valuable reference for professional layout designers.

Title:The Art of Analog LayoutFormat:PaperbackDimensions:672 pages, 9.9 × 8.2 × 1.2 inPublished:June 24, 2005Publisher:Pearson EducationLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0131464108

ISBN - 13:9780131464100


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Agile development is the ability to develop software quickly, in the face of rapidly changing requirements. In order to achieve this agility, we need to employ practices that provide the necessary discipline and feedback. We need to employ design principles that keep our software flexible and maintainable, and we need to know the design patterns that have been shown to balance those principles for specific problems. This book is an attempt to knit all three of these concepts together into a functioning whole. This book describes those principles, patterns, and practices and then demonstrates, how they are applied by walking through dozens of different case studies. More importantly, the case studies are not presented as complete works. Rather, they are designs in progress. You will see the designers make mistakes, and you will observe how they identify the mistakes and eventually correct them. You will see them puzzle over conundrums and worry over ambiguities and trade-offs. You will see the act of design. The Devil Is in the Details This book contains a lot of Java and C++ code. I hope you will carefully read that code since, to a large degree, the code is the point of the book. The code is the actualization of what this book 6~ '' has to say. There is a repeating pattern to this book. It consists of a series of case studies of varying sizes. Some are very small, and some require several chapters to describe. Each case study is preceded by /material that is meant to prepare you for it. For example, the Payroll case study is preceded by chapters describing the object-oriented design principles and patterns used in the case study. The book begins with a discussion of development practices and processes. That discussion is punctuated by a number of small case studies and examples. From there, the book moves on to the topic of design and design principles, and then to some design patterns, more design principles that govern packages, and more patterns. All of these topics are accompanied by case studies. So prepare yourself to read some code and to pore over some UML diagrams. The book you are about to read is very technical, and its lessons, like the devil, are in the details. A Little History Over six years ago, I wrote a book entitled Designing Object-Oriented C++ Applications using the Booch Method. It was something of magnum opus for me, and I was very pleased with the result and with the sales. This book started out as a second edition to Designing, but that's not how it turned out. Very little remains of the original book in these pages. Little more than three chapters have been carried through, and those chapters have been massively changed. The intent, spirit, and many of the lessons of the book are the same. And yet, I've learned a tremendous amount about software design and development in the six years since Designing came out. This book reflects that learning. What a half-decade! Designing came out just before the Internet collided with the planet. Since then, the number of abbreviations we have to deal with has doubled. We have Design Patterns, Java, EJB, RMI, J2EE, XML, XSLT, HTML, ASP, JSP, Servlets, Application Servers, ZOPE, SOAP, C#, .NET, etc., etc. Let me tell you, it's been hard to keep the chapters of this book reasonably current! The Booch Connection In 1997, I was approached by Grady Booch to help write the third edition of his amazingly successful Object-Oriented Analysis and Design with Applications. I had worked with Grady before on some projects, and I had been an avid reader and contributor to his various works, including UML. So I accepted with glee. I asked my good friend Jim Newkirk to help out with the project. Over the next two years, Jim and I wrote a number of chapters for the Booch book. Of course, that effort meant that I could not put as much effort into this book as I would have liked, but I felt that the Booch book was worth the contribution. Besides, this book was really just a second edition of Designing at the time, and my heart wasn't in it. If I was going to say something, I wanted to say something new and different. Unfortunately, that version of the Booch book was not to be. It is hard to find the time to write a book during normal times. During the heady days of the ".com" bubble, it was nearly impossible. Grady got ever busier with Rational and with new ventures like Catapulse. So the project stalled. Eventually, I asked Grady and Addison Wesley if I could have the chapters that Jim and I wrote to include in this book. They graciously agreed. So several of the case study and UML chapters came from that source. The Impact of Extreme Programming In late 1998, XP reared its head and challenged our cherished beliefs about software development. Should we create lots of UML diagrams prior to writing any code, or should we eschew any kind of diagrams and just write lots of code? Should we write lots of narrative documents that describe our design, or should we try to make the code narrative and expressive so that ancillary documents aren't necessary? Should we program in pairs? Should we write tests before we write production code? What should we do? This revolution came at an opportune time for me. During the middle to late 90s, Object Mentor was helping quite a few companies with object-oriented (OO) design and project management issues. We were helping companies get their projects done. As part of that help, we instilled our own attitudes and practices into the teams. Unfortunately, these attitudes and practices were not written down. Rather, they were an oral tradition that was passed from us to our customers. By 1998, I realized that we needed to write down our process and practices so that we could better articulate them to our customers. So, I wrote many articles about process in the C++ Report. These articles missed the mark. They were informative, and in some cases entertaining, but instead of codifying the practices and attitudes that we actually used in our projects, they were an unwitting compromise to values that had been imposed upon me for decades. It took Kent Beck to show me that. The Beck Connection In late 1998, as I was fretting over codifying the Object-Mentor process, I ran into Kent's work on Extreme Programming (XP). The work was scattered through Ward Cunningham's wiki and was mixed with the writings oil many others. Still, with some work and diligence I was able to get the gist of what Kent was talking about. I was intrigued, but skeptical. Some of the things that XP talked about were exactly on target for my concept of a development process. Other things, however, like the lack of an articulated design step, left me puzzled. Kent and I could not have come from more disparate software circumstances. He was a recognized Smalltalk consultant, and I was a recognized C++ consultant. Those two worlds found it difficult to communicate with one' another. There was an almost Kuhnian paradigm gulf between them. Under other circumstances, I would never have asked Kent to write an article for the C++ Report. But the congruence of our thinking about process was able to breech the language gulf. In February of 1999, I met Kent in Munich at the OOP conference. He was giving a talk on XP in the room across from where I was giving a talk on principles of OOD. Being unable to hear that talk, I sought Kent out at lunch. We talked about XP, and I asked him to write an article for the C++ Report. It was a great article about an incident in which Kent and a coworker had been able to make a sweeping design change in a live system in a matter of an hour or so. Over the next several months, I went through the slow process of sorting out my own fears about XP My greatest fear was in adopting a process in which there is no explicit up-front design step. I found myself balking at that. Didn't I have an obligation to my clients, and to the industry as a whole, to teach them that design is important enough to spend time on? Eventually, I realized that I did not really practice such a step myself. Even in all the articles and books I had written about design, Booch diagrams, and UML diagrams, I had always used code as a way to verify that the diagrams were meaningful. In all my customer consulting, I would spend an hour or two helping them to draw diagrams and then I would direct them to explore those diagrams with code. I came to understand that though XP's words about design were foreign (in a Kuhnian sense), the practices behind the words were familiar to me. My other fears about XP were easier to deal with. I had always been a closet pair programmer. XP gave me a way to come out of the closet and revel in my desire to program with a partner. Refactoring, continuous integration, and customer on-site were all very easy for me to accept. They were very close to the way I already advised my customers to work. One practice of XP was a revelation for me. Test-first design sounds innocuous when you first hear it. It says to write test cases before you write production code. All production code is written to make failing test cases pass. I was not prepared for the profound ramifications that writing code this way would have. This practice has completely transformed the way I write software, and transformed it for the better. You can see that transformation in this book. Some of the code written in this book was written before 1999. You won't find test cases for that code. On the other hand, all of the code written after 1999 is presented with test cases, and the test cases are typically presented first. I'm sure you'll note the difference. So, by the fall of 1999 I was convinced that Object Mentor should adopt XP as its process of choice and that I should let go of my desire to write my own process. Kent had done an excellent job of articulating the practices and process of XP, and my own feeble attempts paled in comparison. Organization This book is organized into six major sections followed by several appendices. Section 1: Agile Development This section describes the concept of agile development. It starts with the Manifesto of the Agile Alliance, provides an overview of Extreme Programming (XP), and then goes into many small case studies that illuminate some of the individual XP practices—especially those that have an impact upon the way we design and write code. Section 2: Agile Design The chapters in this section talk about object-oriented software design. The first chapter asks the question, What is Design? It discusses the problem of, and techniques for, managing complexity. Finally, the section culminates with the principles of object-oriented class design. Section 3: The Payroll Case Study This is the largest and most complete case study in the book. It describes the object-oriented design and C++ implementation of a simple batch payroll system. The first few chapters in this section describe the design patterns that the case study encounters. The final two chapters contain the full case study. Section 4: Packaging the Payroll System This section begins by describing the principles of object-oriented package design. It then goes on to illustrate those principles by incrementally packaging the classes from the previous section. Section 5: The Weather Station Case Study This section contains one of the case studies that was originally planned for the Booch book. The Weather Station study describes a company that has made a significant business decision and explains how the Java development team responds to it. As usual, the section begins with a description of the design patterns that will be used and then culminates in the description of the design and implementation. Section 6: The ETS Case Study This section contains a description of an actual project that the author participated in. This project has been in production since 1999. It is the automated test system used to deliver and score the registry examination for the National Council of Architectural Registration Boards. UML Notation Appendices: The first two appendices contains several small case studies that are used to describe the UML notation. Miscellaneous Appendices How to Use This Book If You are a Developer... Read the book cover to cover. This book was written primarily for developers, and it contains the information you need to develop software in an agile manner. Reading the book cover to cover introduces practices, then principles, then patterns, and then it provides case studies that tie them all together. Integrating all this knowledge will help you get your projects done. If You Are a Manager or Business Analyst... Read Section 1, Agile Development. The chapters in this section provide an in-depth discussion of agile principles and practices. They'll take you from requirements to planning to testing, refactoring, and programming. It will give you guidance on how to build teams and manage projects. It will help you get your projects done. If You Want to Learn UML... First read Appendix A, UML Notation 1: The CGI Example. Then read Appendix B, UML Notation II: The STATMUX. Then, read all the chapters in Section 3, The Payroll Case Study. This course of reading will give you a good grounding in both the syntax and use of UML. It will also help you translate between UML and a programming language like Java or C++. If You Want to Learn Design Patterns... To find a particular pattern, use the "List of Design Patterns" on page xxii to find the pattern you are interested in. To learn about patterns in general, read Section 2, Agile Design to first learn about design principles, and then read Section 3, The Payroll Case Study; Section 4, Packaging the Payroll System; Section 5, The Weather Station Case Study; and Section 6, The ETS Case Study. These sections define all the patterns and show how to use them in typical situations. If You Want to Learn about Object-Oriented Design Principles... Read Section 2, Agile Design; Section 3, The Payroll Case Study; and Section 4, Packaging the Payroll System. These chapters will describe the principles of object-oriented design and will show you how to use them. If You Want to Learn about Agile Development Methods... Read Section 1, Agile Development. This section describes agile development from requirements to planning, testing, refactoring, and programming. If You Want a Chuckle or Two... Read Appendix C, A Satire of Two Companies.

Table of Contents

Preface to the Second Edition xvii

Preface to the First Edition xix

Acknowledgments xxi

1 Device Physics 1

1.1 Semiconductors 1

1.1.1. Generation and Recombination 4

1.1.2. Extrinsic Semiconductors 6

1.1.3. Diffusion and Drift 9

1.2 PN Junctions 11

1.2.1. Depletion Regions 11

1.2.2. PN Diodes 13

1.2.3. Schottky Diodes 16

1.2.4. Zener Diodes 18

1.2.5. Ohmic Contacts 19

1.3 Bipolar Junction Transistors 21

1.3.1. Beta 23

1.3.2. I-V Characteristics 24

1.4 MOS Transistors 25

1.4.1. Threshold Voltage 27

1.4.2. I-V Characteristics 29

1.5 JFET Transistors 32

1.6 Summary 34

1.7 Exercises 35

2 Semiconductor Fabrication 37

2.1 Silicon Manufacture 37

2.1.1. Crystal Growth 38

2.1.2. Wafer Manufacturing 39

2.1.3. The Crystal Structure of Silicon 39

2.2 Photolithography 41

2.2.1. Photoresists 41

2.2.2. Photomasks and Reticles 42

2.2.3. Patterning 43

2.3 Oxide Growth and Removal 43

2.3.1. Oxide Growth and Deposition 44

2.3.2. Oxide Removal 45

2.3.3. Other Effects of Oxide Growth and Removal 47

2.3.4. Local Oxidation of Silicon (LOCOS) 49

2.4 Diffusion and Ion Implantation 50

2.4.1. Diffusion 51

2.4.2. Other Effects of Diffusion 53

2.4.3. Ion Implantation 55

2.5 Silicon Deposition and Etching 57

2.5.1. Epitaxy 57

2.5.2. Polysilicon Deposition 59

2.5.3. Dielectric Isolation 60

2.6 Metallization 62

2.6.1. Deposition and Removal of Aluminum 63

2.6.2. Refractory Barrier Metal 65

2.6.3. Silicidation 67

2.6.4. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat 69

2.6.5. Copper Metallization 71

2.7 Assembly 73

2.7.1. Mount and Bond 74

2.7.2. Packaging 77

2.8 Summary 78

2.9 Exercises 78

3 Representative Processes 80

3.1 Standard Bipolar 81

3.1.1. Essential Features 81

3.1.2. Fabrication Sequence 82

Starting Material 82

N-Buried Layer 82

Epitaxial Growth 83

Isolation Diffusion 83


Base Implant 84

Emitter Diffusion 84

Contact 85

Metallization 85

Protective Overcoat 86

3.1.3. Available Devices 86

NPN Transistors 86

PNP Transistors 88

Resistors 90

Capacitors 92

3.1.4. Process Extensions 93

Up-Down Isolation 93

Double-Level Metal 94

Schottky Diodes 94

High-Sheet Resistors 94

Super-Beta Transistors 96

3.2 Polysilicon-Gate CMOS 96

3.2.1. Essential Features 97

3.2.2. Fabrication Sequence 98

Starting Material 98

Epitaxial Growth 98

N-Well Diffusion 98

Inverse Moat 99

Channel Stop Implants 100

LOCOS Processing and Dummy Gate Oxidation 100

Threshold Adjust 101


Polysilicon Deposition and Patterning 102

Source/Drain Implants 102

Contacts 103

Metallization 103

Protective Overcoat 103

3.2.3. Available Devices 104

NMOS Transistors 104

PMOS Transistors 106

Substrate PNP Transistors 107

Resistors 107

Capacitors 109

3.2.4. Process Extensions 109

Double-Level Metal 110

Shallow Trench Isolation 110

Silicidation 111

Lightly Doped Drain (LDD) Transistors 112

Extended-Drain, High-Voltage Transistors 113

3.3 Analog BiCMOS 114

3.3.1. Essential Features 115

3.3.2. Fabrication Sequence 116

Starting Material 116

N-Buried Layer 116

Epitaxial Growth 117

N-Well Diffusion and 117

Base Implant 118

Inverse Moat 118

Channel Stop Implants 119

LOCOS Processing and Dummy Gate Oxidation 119

Threshold Adjust 119

Polysilicon Deposition and Pattern 120

Source/Drain Implants 120

Metallization and Protective Overcoat 120

Process Comparison 121

3.3.3. Available Devices 121

NPN Transistors 121

PNP Transistors 123

Resistors 125

3.3.4. Process Extensions 125

Advanced Metal Systems 126

Dielectric Isolation 126

3.4 Summary 130

3.5 Exercises 131

4 Failure Mechanisms 133

4.1 Electrical Overstress 133

4.1.1. Electrostatic Discharge (ESD) 134

Effects 135

Preventative Measures 135

4.1.2. Electromigration 136

Effects 136

Preventative Measures 137


4.1.3. Dielectric Breakdown 138

Effects 138

Preventative Measures 139

4.1.4. The Antenna Effect 141

Effects 141

Preventative Measures 142

4.2 Contamination 143

4.2.1. Dry Corrosion 144

Effects 144

Preventative Measures 145

4.2.2. Mobile Ion Contamination 145

Effects 145

Preventative Measures 146

4.3 Surface Effects 148

4.3.1. Hot Carrier Injection 148

Effects 148

Preventative Measures 150

4.3.2. Zener Walkout 151

Effects 151

Preventative Measures 152

4.3.3. Avalanche-Induced Beta Degradation 153

Effects 153

Preventative Measures 154

4.3.4. Negative Bias Temperature Instability 154

Effects 155

Preventative Measures 155

4.3.5. Parasitic Channels and Charge Spreading 156

Effects 156

Preventative Measures (Standard Bipolar) 159

Preventative Measures (CMOS and BiCMOS) 162

4.4 Parasitics 164

4.4.1. Substrate Debiasing 165

Effects 166

Preventative Measures 167

4.4.2. Minority-Carrier Injection 169

Effects 169

Preventative Measures (Substrate Injection) 172

Preventative Measures (Cross-Injection) 178

4.4.3. Substrate Influence 180

Effects 180

Preventative Measures 180

4.5 Summary 183

4.6 Exercises 183

5 Resistors 185

5.1 Resistivity and Sheet Resistance 185

5.2 Resistor Layout 187

5.3 Resistor Variability 191

5.3.1. Process Variation 191

5.3.2. Temperature Variation 192

5.3.3. Nonlinearity 193

5.3.4. Contact Resistance 196

5.4 Resistor Parasitics 197

5.5 Comparison of Available Resistors 200

5.5.1. Base Resistors 200

5.5.2. Emitter Resistors 201

5.5.3. Base Pinch Resistors 202

5.5.4. High-Sheet Resistors 202

5.5.5. Epi Pinch Resistors 205

5.5.6. Metal Resistors 206

5.5.7. Poly Resistors 208

5.5.8. NSD and PSD Resistors 211

5.5.9. N-Well Resistors 211

5.5.10. Thin-Film Resistors 212

5.6 Adjusting Resistor Values 213

5.6.1. Tweaking Resistors 213

Sliding Contacts 214

Sliding Heads 215

Trombone Slides 215

Metal Options 215

5.6.2. Trimming Resistors 216

Fuses 216

Zener Zaps 219

EPROM Trims 221

Laser Trims 222

5.7 Summary 223

5.8 Exercises 224

6 Capacitors and Inductors 226

6.1 Capacitance 226

6.1.1. Capacitor Variability 232

Process Variation 232

Voltage Modulation and Temperature Variation 233

6.1.2. Capacitor Parasitics 235

6.1.3. Comparison of Available Capacitors 237

Base-Emitter Junction Capacitors 237

MOS Capacitors 239

Poly-Poly Capacitors 241

Stack Capacitors 243

Lateral Flux Capacitors 245

High-Permittivity Capacitors 246

6.2 Inductance 246

6.2.1. Inductor Parasitics 248

6.2.2. Inductor Construction 250

Guidelines for Integrating Inductors 251

6.3 Summary 252

6.4 Exercises 253

7 Matching of Resistors and Capacitors 254

7.1 Measuring Mismatch 254

7.2 Causes of Mismatch 257

7.2.1. Random Variation 257

Capacitors 258

Resistors 258

7.2.2. Process Biases 260

7.2.3. Interconnection Parasitics 261

7.2.4. Pattern Shift 263

7.2.5. Etch Rate Variations 265

7.2.6. Photolithographic Effects 267

7.2.7. Diffusion Interactions 268

7.2.8. Hydrogenation 270

7.2.9. Mechanical Stress and Package Shift 271

7.2.10. Stress Gradients 274

Piezoresistivity 274

Gradients and Centroids 275

Common-Centroid Layout 277

Location and Orientation 281

7.2.11. Temperature Gradients and Thermoelectrics 283

Thermal Gradients 285

Thermoelectric Effects 287

7.2.12. Electrostatic Interactions 288

Voltage Modulation 288

Charge Spreading 292

Dielectric Polarization 293

Dielectric Relaxation 294

7.3 Rules for Device Matching 295

7.3.1. Rules for Resistor Matching 296

7.3.2. Rules for Capacitor Matching 300

7.4 Summary 303

7.5 Exercises 304

8 Bipolar Transistors 306

8.1 Topics in Bipolar Transistor Operation 306

8.1.1. Beta Rolloff 308

8.1.2. Avalanche Breakdown 308

8.1.3. Thermal Runaway and Secondary Breakdown 310

8.1.4. Saturation in NPN Transistors 312

8.1.5. Saturation in Lateral PNP Transistors 315

8.1.6. Parasitics of Bipolar Transistors 318

8.2 Standard Bipolar Small-Signal Transistors 320

8.2.1. The Standard Bipolar NPN Transistor 320

Construction of Small-Signal NPN Transistors 322

8.2.2. The Standard Bipolar Substrate PNP Transistor 326

Construction of Small-Signal Substrate PNP Transistors 328

8.2.3. The Standard Bipolar Lateral PNP Transistor 330

Construction of Small-Signal Lateral PNP Transistors 332

8.2.4. High-Voltage Bipolar Transistors 337

8.2.5. Super-Beta NPN Transistors 340

8.3 CMOS and BiCMOS Small-Signal Bipolar Transistors 341

8.3.1. CMOS PNP Transistors 341

8.3.2. Shallow-Well Transistors 345

8.3.3. Analog BiCMOS Bipolar Transistors 347

8.3.4. Fast Bipolar Transistors 349

8.3.5. Polysilicon-Emitter Transistors 351

8.3.6. Oxide-Isolated Transistors 354

8.3.7. Silicon-Germanium Transistors 356

8.4 Summary 358

8.5 Exercises 358

9 Applications of Bipolar Transistors 360

9.1 Power Bipolar Transistors 361

9.1.1. Failure Mechanisms of NPN Power Transistors 362

Emitter Debiasing 362

Thermal Runaway and Secondary Breakdown 364

Kirk Effect 366

9.1.2. Layout of Power NPN Transistors 368

The Interdigitated-Emitter Transistor 369

The Wide-Emitter Narrow-Contact Transistor 371

The Christmas-Tree Device 372

The Cruciform-Emitter Transistor 373

Power Transistor Layout in Analog BiCMOS 374

Selecting a Power Transistor Layout 376

9.1.3. Power PNP Transistors 376

9.1.4. Saturation Detection and Limiting 378

9.2 Matching Bipolar Transistors 381

9.2.1. Random Variations 382

9.2.2. Emitter Degeneration 384

9.2.3. NBL Shadow 386

9.2.4. Thermal Gradients 387

9.2.5. Stress Gradients 391

9.2.6. Filler-Induced Stress 393

9.2.7. Other Causes of Systomatic Mismatch 395

9.3 Rules for Bipolar Transistor Matching 396

9.3.1. Rules for Matching Vertical Transistors 397

9.3.2. Rules for Matching Lateral Transistors 402

9.4 Summary 402

9.5 Exercises 403

10 Diodes 406

10.1 Diodes in Standard Bipolar 406

10.1.1. Diode-Connected Transistors 406

10.1.2. Zener Diodes 409

Surface Zener Diodes 410

Buried Zeners 412

10.1.3. Schottky Diodes 415

10.1.4. Power Diodes 420

10.2 Diodes in CMOS and BiCMOS Processes 422

10.2.1. CMOS Junction Diodes 422

10.2.2. CMOS and BiCMOS Schottky Diodes 423

10.3 Matching Diodes 425

10.3.1. Matching PN Junction Diodes 425

10.3.2. Matching Zener Diodes 426

10.3.3. Matching Schottky Diodes 428

10.4 Summary 428

10.5 Exercises 429

11 Field-Effect Transistors 430

11.1 Topics in MOS Transistor Operation 431

11.1.1. Modeling the MOS Transistor 431

Device Transconductance 432

Threshold Voltage 434

11.1.2. Parasitics of MOS Transistors 438

Breakdown Mechanisms 440

CMOS Latchup 442

Leakage Mechanisms 443

11.2 Constructing CMOS Transistors 446

11.2.1. Coding the MOS Transistor 447

Width and Length 448

11.2.2. N-Well and P-Well Processes 449

11.2.3. Channel Stop Implants 452

11.2.4. Threshold Adjust Implants 453

11.2.5. Scaling the Transistor 456

11.2.6. Variant Structures 459

Serpentine Transistors 461

Annular Transistors 462

11.2.7. Backgate Contacts 464

11.3 Floating-Gate Transistors 467

11.3.1. Principles of Floating-Gate Transistor Operation 469

11.3.2. Single-Poly EEPROM Memory 472

11.4 The JFET Transistor 474

11.4.1. Modeling the JFET 474

11.4.2. JFET Layout 476

11.5 Summary 479

11.6 Exercises 479

12 Applications of MOS Transistors 482

12.1 Extended-Voltage Transistors 482

12.1.1. LDD and DDD Transistors 483

12.1.2. Extended-Drain Transistors 486

Extended-Drain NMOS Transistors 487

Extended-Drain PMOS Transistors 488

12.1.3. Multiple Gate Oxides 489

12.2 Power MOS Transistors 491

12.2.1. MOS Safe Operating Area 492

Electrical SOA 493

Electrothermal SOA 496

Rapid Transient Overload 497

12.2.2. Conventional MOS Power Transistors 498

The Rectangular Device 499

The Diagonal Device 500

Computation of 501 RM

Other Considerations 502

Nonconventional Structures 503

12.2.3. DMOS Transistors 505

The Lateral DMOS Transistor 506

RESURF Transistors 508

The DMOS NPN 510

12.3 MOS Transistor Matching 511

12.3.1. Geometric Effects 513

Gate Area 513

Gate Oxide Thickness 514

Channel Length Modulation 515

Orientation 515

12.3.2. Diffusion and Etch Effects 516

Polysilicon Etch Rate Variations 516

Diffusion Penetration of Polysilicon 517

Contacts Over Active Gate 518

Diffusions Near the Channel 518

PMOS versus NMOS Transistors 519

12.3.3. Hydrogenation 520

Fill Metal and MOS Matching 521

12.3.4. Thermal and Stress Effects 521

Oxide Thickness Gradients 522

Stress Gradients 522

Thermal Gradients 522

12.3.5. Common-Centroid Layout of MOS Transistors 523

12.4 Rules for MOS Transistor Matching 528

12.5 Summary 531

12.6 Exercises 531

13 Special Topics 534

13.1 Merged Devices 534

13.1.1. Flawed Device Mergers 535

13.1.2. Successful Device Mergers 539

13.1.3. Low-Risk Merged Devices 541

13.1.4. Medium-Risk Merged Devices 542

13.1.5. Devising New Merged Devices 544

13.1.6. The Role of Merged Devices in Analog BiCMOS 544

13.2 Guard Rings 545

13.2.1. Standard Bipolar Electron Guard Rings 546

13.2.2. Standard Bipolar Hole Guard Rings 547

13.2.3. Guard Rings in CMOS and BiCMOS Designs 548

13.3 Single-level Interconnection 551

13.3.1. Mock Layouts and Stick Diagrams 551

13.3.2. Techniques for Crossing Leads 553

13.3.3. Types of Tunnels 555

13.4 Constructing the Padring 557

13.4.1. Scribe Streets and Alignment Markers 557

13.4.2. Bondpads,Trimpads, and Testpads 558

13.5 ESD Structures 562

13.5.1. Zener Clamp 563

13.5.2. Two-Stage Zener Clamps 565

13.5.3. Buffered Zener Clamp 566

13.5.4. Clamp 568

13.5.5. Clamp 569

13.5.6. Antiparallel Diode Clamps 570

13.5.7. Grounded-Gate NMOS Clamps 570

13.5.8. CDM Clamps 572

13.5.9. Lateral SCR Clamps 573

13.5.10. Selecting ESD Structures 575

13.6 Exercises 578

14 Assembling the Die 581

14.1 Die Planning 581

14.1.1. Cell Area Estimation 582

Resistors 582

Capacitors 582

Vertical Bipolar Transistors 583

Lateral PNP Transistors 583

MOS Transistors 583

MOS Power Transistors 584

Computing Cell Area 584

14.1.2. Die Area Estimation 584

14.1.3. Gross Profit Margin 587

14.2 Floorplanning 588

14.3 Top-Level Interconnection 594

14.3.1. Principles of Channel Routing 594

14.3.2. Special Routing Techniques 596

Kelvin Connections 597

Noisy Signals and Sensitive Signals 598

14.3.3. Electromigration 600

14.3.4. Minimizing Stress Effects 603

14.4 Conclusion 604

14.5 Exercises 605


A. Table of Acronyms Used in the Text 607

B. The Miller Indices of a Cubic Crystal 611

C. Sample Layout Rules 614

D. Mathematical Derivations 622

E. Sources for Layout Editor Software 627

Index 628