Transactions on High-Performance Embedded Architectures and Compilers II by Per StenstrTransactions on High-Performance Embedded Architectures and Compilers II by Per Stenstr

Transactions on High-Performance Embedded Architectures and Compilers II

byPer StenstrEditorDavid Whalley

Paperback | April 22, 2009

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This book contains extended versions of key papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007). It also covers such topics as microarchitecture, code generation, and performance modeling.

Title:Transactions on High-Performance Embedded Architectures and Compilers IIFormat:PaperbackDimensions:327 pages, 23.5 × 15.5 × 1.73 inPublished:April 22, 2009Publisher:Springer-Verlag/Sci-Tech/TradeLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:3642009034

ISBN - 13:9783642009037

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Table of Contents

Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation through Branch History Matching.- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.- Regular Papers.- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.- Fetch Gating Control through Speculative Instruction Window Weighting.- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.- Linux Kernel Compaction through Cold Code Swapping.- Complexity Effective Bypass Networks.- A Context-Parameterized Model for Static Analysis of Execution Times.- Reexecution and Selective Reuse in Checkpoint Processors.- Compiler Support for Code Size Reduction Using a Queue-Based Processor.- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.