Unleash the System On Chip using FPGAs and Handel C by Rajanish K. KamatUnleash the System On Chip using FPGAs and Handel C by Rajanish K. Kamat

Unleash the System On Chip using FPGAs and Handel C

byRajanish K. Kamat, Santosh A. Shinde, Vinod G Shelake

Paperback | October 19, 2010

Pricing and Purchase Info

$155.29 online 
$168.95 list price save 8%
Earn 776 plum® points

Prices and offers may vary in store


In stock online

Ships free on orders over $25

Not available in stores


Unleash the System On Chip using FPGAs and Handel C is an attempt to empower the design community by delivering the 'know-how' developed by the authors with their vast experience in VLSI design. The book effectively showcases carving of SoC through (1) 'Concept to Product' approach, (2) 'C' based methodology at higher level of abstraction, (3) 'Bottom up & design reuse philosophy', (4) Edifying with the soft IP cores in Handel C, (5) Pragmatic approach to bridge the gap between design metrics, (6) Synergical approach for combining reconfiguration of FPGAs with soft IP cores, (7) 'Partial reconfiguration', 'concurrent hardware software SoC realization' through Xilinx EDK, (8) 'Network on Chip', (9) Co-simulation & integration of third party tools, (10) Development of interesting case studies such as fuzzy logic controllers, arithmetic on chip etc., (11) Cores for control system using 'picoblaze', (12) Actual screeshots & step by step design flow.35 Handel C cores, 7 chapters & 128 selected references will facilitate in getting acquainted with innovative design methodologies of building the SoCs & opens a new door of research and development & infinite set of futures in this ever-growing technology of this century.
Title:Unleash the System On Chip using FPGAs and Handel CFormat:PaperbackDimensions:200 pagesPublished:October 19, 2010Publisher:Springer NetherlandsLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:9048181119

ISBN - 13:9789048181117

Look for similar items by category:


Table of Contents

Preface. Foreword. Acknowledgements.Chapter 1: Introduction1.1 Prologue1.2 Exceptional Attributes of the  SoC Technology1.3 Classical taxonomy: a holistic perspective extended towards  Integrated Circuits Classification1.4 System on Chip (SoC) Term and Scope1.5 Constituents of SoC1.6 Sprawling Growth of SoC market1.7 Choosing the platform, ASIC Vs FPGAs1.8 FPGA based Programmable SoC1.9 Orientation of the BookChapter 2: Familiarizing with Handel C2.1 EDA Tools i.e. Computer Aids for VLSI Design2.2 Background of Hardware Description Languages2.3 Expressing abstraction at higher levels2.4 Where C stands amidst the well established HDLs?2.5 Introducing Handel C 2.6 Top Down or Bottom up?2.7 Handel C: A boon for Software Professionals2.8 Handel C vs ANSI C2.9 Handel C Design FlowChapter 3: Sequential logic Design3.1 Design Philosophy of Sequential Logic3.2 D flip-flop3.3 Latch3.4 Realization of JK Flip-Flop3.5 Cell of  Hex counter for Counter Applications3.6 Realization of Shift Register for SoC3.7 LFSR Core for Security Applications in SoC3.8 Clock Scaling and Delay Generation in SoC3.9 SoC Data Queuing using FIFO3.10 Implementation of Stack though LIFO3.11 Soft IP core for Hamming CodeChapter 4: Combinational Logic Design4.1 Introduction4.2 Design Metrics for the Combinational Logic Circuits: SoC Perspective4.3 Core of "2 to 4 decoder"4.4 "3 to 8 decoder" using hierarchical approach4.5 Priority Encoder 4 to 24.6 Soft IP Core of "7 to 3 encoder" Implementation4.7 IP core of 'Parity generator' for Communication Applications4.8 IP Core for Parity checker and error detection for Internet Protocol4.9 BCD TO Seven Segment converter4.10 Core of Binary to Gray Converter and Applications4.11 Realization of IP Core of Gray to Binary Converter4.12  Designing Barrel Shifters Chapter 5: Arithmetic core design and Design Reuse of  Soft IP Cores5.1 Design Reuse Philosophy5.2 Advantages of on chip arithmetic5.3 Designing Half adder in Handel C 5.4 Full Adder 5.5 Ripple Carry Adder 5.6 Booth Algorithm and its realization on FPGA5.7 Building ALU in Handel C5.7 Third Party Tool Interface with Handel C5.8 Xilinx EDK Interface with Cores developed through Handel CChapter 6: Rapid Prototyping of the Soft IP cores on FPGA6.1 Prototyping Philosophy6.2 Rapid Design of Fuzzy Controller using Handel C6.3 Packet Processor Core for Inculcating Embedded Network Security using Mixed Design Flow6.4. A Linear Congruential Generator (LCG) SoC6.5 Implementation of Reusable Soft IP core of Blowfish CipherChapter 7: Soft Processor Core for Accelerated Embedded Design7.1 Building SoC for temperature control application using Picoblaze7.2 Hardware Software Codesign of SoC with built in Position AlgorithmReferences. List of Tables. List of Figures. List of Programs.