VHDL Coding and Logic Synthesis with Synopsys

Other | August 1, 2000

byLee, Weng Fook, Weng Fook Lee

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This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.

Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.


* First practical guide to using synthesis with Synopsys
* Synopsys is the #1 design program for IC design

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This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.Synopsys is the dominant computer-aided circuit design program in the wo...

Weng Fook Lee is a distinguished principal design engineer at Advanced Micro Devices, Inc. (AMD) and has earned the reputation as a respected synthesis expert. He has vast experience designing ASIC with VHDL. He is an expert at synthesizing circuits tweaked for maximum performance and minimal area utilization, and at developing and imp...

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Format:OtherDimensions:392 pages, 1 × 1 × 1 inPublished:August 1, 2000Publisher:Academic PressLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0080520502

ISBN - 13:9780080520506

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Extra Content

Table of Contents

List of Figures.
List of Tables.
List of Examples.
Preface.
Acknowledgement.
Trademarks.

I. VHDL CODING
1. Introduction.
2. VHDL Simulation and Synthesis Flow.
3. Synthesizable Code for Basic Logic Components.
4. Signal Versus Variable.
5. Examples of Complex Synthesizable Code.
6. Pipeline Microcontroller Synthesizable Design.

II. LOGIC SYNTHESIS WITH SYNOPSYS.
7. Timing Considerations in Design.
8. VHDL Synthesis with Timing Constraints.
9. GTECH Instantiation.
10. DesignWare Library.
11. Testability Issues in Synthesis.
12. FPGA Synthesis.
13. Synthesis Links to Layout.
14. Design Guideline to Follow for Efficient Synthesis.
15. Appendix A (STD_LOGIC_1164 Library).
16. Appendix B (Shifter Synthesis Results).
17. Appendix C (Counter Synthesis Results).
18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation).
19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6).
20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6).

Glossary.

Bibliography.

Index.