Microprocessors and Interfacing by N Senthil KumarMicroprocessors and Interfacing by N Senthil Kumar

Microprocessors and Interfacing

byN Senthil Kumar, M. Saravanan, S. Jeevananthan

Paperback | June 23, 2012

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Microprocessors and Interfacing is a textbook for undergraduate engineering students who study a course on various microprocessors, its interfacing, programming and applications.The book in eighteen chapters provides a very brief overview of 8085 processors, followed by a detailed discussion of 8086 architecture, programming and interfacing concepts. The book also provides a brief treatment of 8088 processors bringing out its architectural difference in relation to 8086.The thrust of this book is on 8086 processors. Subsequently, the book discusses the 8-bit 8051 and 16-bit 8096 microcontrollers. The last chapter on advanced processors briefs on 80186, 80286, 80386, 80486, Pentium, PowerPC, PIC, RISCand CISC, SUN SPARC and ARM microcontrollers.Providing a balance between theory and practice, the book is interspersed with complete ALP codes, review questions, programming and design based exercises.
Dr N Senthil Kumar is Professor in the Department of Electricaland Electronics Engineering at Mepco Schlenk Engineering College, Sivakasi, Tamilnadu. He has more than 20 years of active teaching and research experience. Dr M Saravanan is Professor in the Department of Electricaland Electronics Engineering at Thiagarajar College of En...
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Title:Microprocessors and InterfacingFormat:PaperbackDimensions:720 pages, 9.84 × 5.91 × 0.03 inPublished:June 23, 2012Publisher:Oxford University PressLanguage:English

The following ISBNs are associated with this title:

ISBN - 10:0198079060

ISBN - 13:9780198079064

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Table of Contents

Preface1. Microprocessors-Evolution and Introduction1.1 Introduction1.2 Explanation of Basic Terms1.3 Microprocessors and Microcontrollers1.4 Microprocessor-based System1.5 Origin of Microprocessors1.5.1 First generation (1971-1973)1.5.2 Second generation (1974-1978)1.5.3 Third generation (1978-1980)1.5.4 Fourth generation (1981-1995)1.5.5 Fifth generation (1995-till date)1.5.6 Timeline of microprocessor evolution1.6 Classification of Microprocessors1.7 Types of Memory1.8 Input and Output Devices1.9 Technology Improvements Adapted to Microprocessors And Computers1.10 Architecture and signals of 80851.11 Instruction set of 80851.12 Memory and I/O interfacing with 80851.13 Interrupt structure of 80852. Methods of data transfer and serial transfer protocols2.1 Data Transfer Mechanisms2.2 Memory-mapped and I/O-mapped Data Transfer2.3 Programmed Data Transfer2.4 Direct Memory Access2.5 Parallel Data Transfer2.5.1 PCI bus2.6 Serial Data transfer2.6.1 Introduction to RS-232 standard2.6.2 Introduction to RS-485 standard2.6.3 GPIB/IEEE 488 standards2.6.4 USBPART 1: INTEL 8086-16-BIT MICROPROCESSORS3. Intel 8086 Microprocessor architecture, features, and signals3.1 Introduction 4193.2 Architecture of 80863.2.1 Execution unit3.2.2 Bus interface unit3.2.3 Differences between 8086 and 80883.3 Accessing Memory Locations3.4 Pin Details of 80863.4.1 Function of pins common to minimum and maximum modes3.4.2 Function of pins used in minimum mode3.4.3 Function of pins used in maximum mode4. Addressing modes, instruction set, and Programming of 80864.1 Addressing Modes in 80864.1.1 Register addressing mode4.1.2 Immediate addressing mode4.1.3 Data memory addressing modes4.1.4 Program memory addressing modes4.1.5 Stack memory addressing mode4.2 Segment Override Prefix4.3 Instruction Set of 80864.3.1 Data transfer instructions4.3.2 Arithmetic instructions4.3.3 Logical instructions4.3.4 Flag manipulation instructions4.3.5 Control transfer instructions4.3.6 Shift/rotate instructions4.3.7 String instructions4.3.8 Machine or processor control instructions4.4 8086 Assembly Language Programming4.4.1 Writing 8086 programs using line assembler4.4.2 8086 Assembler directives4.4.3 Writing assembly language programs using MASM4.5 Program Development Process4.6 Modular Programming4.6.1 CALL Instruction:4.6.2 RET instruction4.6.3 MACRO4.6.3.1 Illustrative Example5. 8086 interrupts5.1 Introduction5.2 Interrupt Types in 80865.3 Processing of Interrupts by 80865.4 Dedicated Interrupt Types in 80865.4.1 Type 00H or divide-by-zero interrupts5.4.2 Type 01H, single step, or trap interrupt5.4.3 type 02H or NMI interrupt5.4.4 Type 03H or one-byte INT interrupt5.4.5 type 04H or overflow interrupt5.5 Software Interrupts-Types 00h-FFH5.6 INTR Interrupts-Types 00h-FFH5.7 Priority among 8086 Interrupts5.8 Interrupt Service Routines5.9 Bios Interrupts or Function Calls5.9.1 INT 10H5.9.2 INT 11H5.9.3 INT 12H5.9.4 INT 13H5.9.5 INT 14H5.9.6 INT 15H5.9.7 INT 16H5.9.8 INT 17H5.10. Interrupt Handlers5.11 DOS Services: int 21h5.11.1 Example_15.11.2 Example_25.12 System Calls: BIOS Services5.12.1 Print Screen Service: INT 05h5.12.2 Video Services: INT 10h5.12.3 Keyboard Services: int 16h5.12.3.1 Example_15.12.3.2 Example_25.12.4 Printer Services: int 17h5.12.4.1 Example_15.12.4.2 Example_26. Basic Memory and I/O interfacing with 80866.1 Physical Memory Organization in 80866.2 Formation of System Bus6.3 Interfacing RAM and EPROM Chips using only Logic Gates6.4 Interfacing Ram/EPROM Chips using Decoder IC and Logic Gates6.5 I/O Interfacing6.5.1 I/O instructions in 80866.5.2 I/O-mapped and memory-mapped I/O6.6 Interfacing 8-bit input device with 80866.6.1 Assigning 8-bit address to 8-bit input device using address decoder having only logic gates6.6.2 Assigning 8-bit address to 8-bit input device using address decoder IC 74LS1386.6.3 Assigning 16-bit address to 8-bit DIP switch using address decoder having only logic gates6.7 Interfacing 8-bit Output Device with 80866.8 Interfacing 8-bit and 16-bit I/O Devices or Ports with 80867. Features and interfacing of programmable peripheral devices with 80867.1 Intel 8255 Programmable Peripheral Interface7.1.1 Features of 82557.1.2 Block diagram of Intel 82557.1.3 Operating modes and control words of 82557.1.4 Configuring examples7.1.5 Other programmable peripheral Interface ICs -8155 and 87557.2 Interfacing Switches and LEDs7.3 Interfacing Seven-segment Displays7.4 Traffic Light Control7.5 Interfacing Analog-to-digital Converters7.6 Interfacing Digital-to-analog Converters7.6.1 Square wave generation7.6.2 Staircase waveform generation7.6.3 Ramp waveform generation7.6.4 Waveform generation using stored data7.7 Interfacing Stepper Motors7.8 Interfacing Intelligent LCDs7.9 Keyboard and Display Interface IC 82797.9.1 Matrix keyboard7.9.2 Multiplexed display7.9.3 Features, block diagram, and pin details of 82797.9.4 Programming of 82797.9.5 Display interface using 8279 with 80867.9.6 Keyboard interface using 8279 with 80867.10 Intel Timer IC 82537.10.1 Features of IC 82537.10.2 Block diagram of IC 8253 and pin details7.10.3 Operating modes and control word of IC 82537.10.4 Interfacing IC 8253 with 80867.11 Introduction to Serial Communication7.11.1 Features and details of 8251 USART7.11.2 Control words7.11.3 Interfacing 8251 with 80867.12 8259 Programmable Interrupt Controller7.12.1 Features and architecture of 82597.12.2 Pin diagram and details of 82597.12.3 Initialization of 82597.12.4 Operation of 82597.12.5 Interfacing 8259 with 80867.13 8237 DMA Controller7.13.1 Features, pin details, and architecture of 82377.13.2 DMA initialization and operation7.13.3 Operation of 8237 with 80867.14 Interfacing Printer with 80867.15 Interfacing CRT Terminal with 80868. Multiprocessor configuration8.1 Introduction8.2 Multiprocessor System-Need and Advantages8.3 Different Configurations of Multiprocessor System8.3.1 Coprocessor and closely-coupled configurations8.3.2 Loosely-coupled configuration8.4 Bus Arbitration in Loosely-coupled Multiprocessor System8.4.1 Daisy chaining8.4.2 Polling8.4.3 Independent requesting8.5 Interconnection Topologies in a Multiprocessor System8.5.1 Shared bus architecture8.5.2 Multi-port memory8.5.3 Linked input/output8.5.4 Crossbar switching8.6 Physical Interconnections between Processors in a Multiprocessor System8.6.1 Star configuration8.6.2 Ring or loop configuration8.6.3 Completely-connected configuration8.6.4 Regular topology8.6.5 Irregular topology8.7 Operating System Used in a Multiprocessor System8.8 Typical Multiprocessor System having 8086 and 80878.8.1 Architecture of 80878.8.2 Pin details of 80878.8.3 Interconnection of 8087 with 80868.8.4 Data types of 80878.9 Typical Multiprocessor System having 8086 and 80898.9.1 Pin details of 80898.9.2 Local and remote operation of 80898.9.3 8089 (IOP) architecture8.9.4 Communication between CPU (8086) and IOP (8089)9. 8086-BASED SYSTEMS9.1 Introduction9.2 8086 in Minimum Mode Configuration9.2.1 Formation of separate address bus and data bus in 80869.2.2 Formation of buffered address bus and data bus in 80869.2.3 Connection of 8284A with 80869.3 8086 in Maximum Mode Configuration9.4 8086 System Bus Timings9.4.1 Timing diagrams for general bus operation in minimum mode9.4.2 Timing diagrams for general bus operation in maximum mode9.4.3 Interrupt acknowledgement (INTA) timing9.4.4 Bus request and bus grant timing9.5 Design of Minimum Mode 8086-based SystemPART 2: INTEL 8051 MICROCONTROLLERS10. Introduction to 8051 Microcontrollers10.1 Introduction10.2 Intel's MCS-51 Series Microcontrollers10.3 Intel 8051 Architecture10.4 Memory Organization10.5 Internal RAM Structure10.5.1 Special function registers10.5.2 Processor status word10.6 Power Control in 805110.6.1 Idle mode10.6.2 Power down mode10.7 Stack Operation11. 8051 instruction set and programming11.1 Introduction11.2 Addressing Modes of 805111.2.1 Immediate addressing11.2.2 Register direct addressing11.2.3 Memory direct addressing11.2.4 Memory indirect addressing11.2.5 Indexed addressing11.3 Instruction Set of 805111.3.1 Data transfer instructions11.3.2 Arithmetic instructions11.3.3 Logical instructions11.3.4 Branching instructions11.3.5 Bit manipulation instructions11.4 Some Assembler Directives11.5 Programming Examples using 8051 Instruction Set12. Hardware features of 805112.1 Introduction12.2 Parallel Ports in 805112.2.1 Structure of port 112.2.2 Structure of ports 0 and 212.2.3 Structure of port 312.3 External Memory Interfacing in 805112.3.1 Program memory interfacing12.3.2 Data memory interfacing12.3.3 Timing diagram for external program and data memory access12.4 8051 Timers12.4.1 Timer SFRs12.4.2 Timer operating modes12.4.3 Timer control and operation12.4.4 Using timers as counters12.4.5 Programming examples12.5 8051 Interrupts12.5.1 Interrupt sources and interrupt vector addresses12.5.2 Enabling and disabling of interrupts12.5.3 Interrupt priorities and polling sequence12.5.4 Timing of interrupts12.5.5 Programming examples12.6 8051 Serial Ports12.6.1 Serial port control Sfrs12.6.2 Operating modes12.6.3 Programming serial port13. Interface examples13.1 Interfacing 8255 with 805113.2 Interfacing of Push Button Switches and LEDs13.3 Interfacing of Seven-segment Displays13.4 Interfacing ADC Chip13.5 Interfacing DAC Chip13.5.1 Square wave generation13.5.2 Staircase wave generation13.5.3 Ramp wave generation13.5.4 Sine wave generation13.6 Interfacing Matrix Keypad13.7 Interfacing Stepper Motor with 805113.8 Interfacing LCD with 805113.9 Interfacing DC Motors/Servomotors13.10 Microcontroller Application Example-Stopwatch13.11 Microcontroller Application Example-Traffic light control13.12 Microcontroller Application Example-Thermometer13.13 RTC Interfacing using I2C Standard13.13.1 Details of I2C bus13.13.2 8051 Subroutines used to implement I2C bus13.13.3 DS1307-Serial I2C real-time clock IC13.14 Washing Machine control13.15 Elevator / Lift interfacePART 3: INTEL 8096-16-BIT MICROCONTROLLERS14. OVERVIEW OF INTEL 8096 MICROCONTROLLERS14.1 Introduction14.2 Features of Intel 8096 Microcontroller14.3 Functional Block Diagram of Intel 8096 Microcontroller14.3.1 CPU section14.3.2 8096 CPU buses14.3.3 Register arithmetic and logical unit14.3.4 Temporary register14.3.5 Register file14.3.6 Program status word14.3.7 Memory controller14.3.8 Internal timing14.3.9 I/O section 59214.4 Memory Structure of 809614.5 Power Down Mode of CPU15. 8096 INSTRUCTION SET AND PROGRAMMING15.1 8096 Operand Types15.2 Addressing Modes15.2.1 Register direct addressing15.2.2 Indirect addressing15.2.3 Indirect addressing with auto increment15.2.4 Immediate addressing15.2.5 Short-indexed addressing15.2.6 Long-indexed addressing15.2.7 Zero register addressing15.2.8 Stack pointer register addressing15.3 Classification of Instructions15.3.1 Data transfer instructions15.3.2 Arithmetic and logical instructions15.3.3 Shift/rotate instructions15.3.4 Branching instructions15.4 Complete 8096 Instruction Set15.5 Programming Examples using 8096 Instruction Set16. HARDWARE FEATURES OF 809616.1 Parallel Ports in 8096 and their Structure16.1.1 Port 016.1.2 Port 116.1.3 Port 216.1.4 Port 3 and Port 416.2 Control and Status Registers16.2.1 Input/output control register 016.2.2 Input/output control register 116.2.3 Input/output status register 016.2.4 Input/output status register 1 62016.3 Timers16.3.1 Timer 116.3.2 Timer 216.4 Interrupts16.4.1 Interrupt sources16.4.2 Polling routine16.4.3 Vectored interrupt16.4.4 Interrupt control16.4.5 Interrupt pending register16.4.6 Interrupt mask register16.4.7 Global disable16.4.8 Program status word (PSW)16.5 Serial Ports16.5.1 Operating modes of serial port16.5.2 Serial port control/status registers16.5.3 Determining baud rate16.5.4 Program for serial port data reception16.6 Analog-to-digital Converter16.7 Digital-to-analog Converter16.8 High Speed Input Unit16.8.1 HSI interrupts16.8.2 Programming HSI16.9 High Speed Output Unit16.9.1 HSO status16.10 Memory Expansion16.10.1 Single chip mode16.10.2 Expanded mode16.10.3 Choice of bus width16.10.4 Bus control16.10.5 ROM/EPROM lockPART 4: ADVANCED TRENDS17. MICROPROCESSOR SYSTEM DEVELOPMENTS AND RECENT TRENDS17.1 Introduction17.2 Microcontroller Features and Developments17.3 Microprocessor Development Systems17.3.1 In-system programming17.3.2 Debugger17.3.3 Emulator17.4 Cross Compiler for 805117.5 Programming 8051 in C Language18. ADVANCED MICROPROCESSORS AND MICROCONTROLLERS18.1 Introduction18.2 80186 Microprocessor18.2.1 Architecture18.2.2 Instruction set of 8018618.3 80286 Microprocessor18.3.1 Architecture18.3.2 Register organization and real or protected addressing in 8028618.3.3 Privilege levels in protected mode of operation18.3.4 Descriptor cache or program-invisible registers18.3.5 Accessing memory using GDT and LDT18.3.6 Multitasking in 8028618.3.7 Addressing modes and new instructions in 8028618.3.7 Flag register18.4 80386 Microprocessor18.4.1 Architecture of 8038618.4.2 Register organization in 8038618.4.3 Instruction set of 8038618.4.4 Addressing memory in protected mode18.4.5 Physical memory organization in 8038618.4.6 Paging mechanism in 8038618.5 80486 Microprocessor18.6 Pentium Microprocessor18.6.1 Architecture of Pentium18.6.2 Protected mode operation of Pentium18.6.3 Addressing modes in Pentium18.6.4 Paging mechanism in Pentium18.7 Other Versions of Pentium18.7.1 Pentium pro processor18.7.2 Pentium II processor18.7.3 Pentium III processor18.7.4 Pentium 4 processor18.8 Operating Modes of Advance Processors18.9 Mode Transition18.10 Memory management in Protected Mode18.11 Segment Descriptor18.12 Protection: Purpose18.12.1 Type checking18.12.2 Limit checking/Restriction of addressable domain18.12.3 Privilege Levels: Check for Data Access in Data Segment18.12.3.2 Check for Data Access in Code Segment18.12.3.3 Check for Control Transfers18.12.3.4 Stack Switching18.13 Protected Mode Instructions18.14 Multitasking18.14.1 Time Slice Scheduling18.14.2 Bit Permission Map18.14.3 Priority Based Scheduling:18.14.4 Task Switching in Protected Mode18.14.4.1 Task-State Segment (TSS) TSS Descriptor18.14.4.3 Task gate Descriptor18.14.4.4 Context/ TASK SWITCHING19. Embedded Systems19.1 Introduction19.1.1 Characteristics of Embedded Systems19.1.2 Design metric19.1.3 Evolution of Embedded System19.1.4 Design Technology19.1.4.1 Compilation/Synthesis19.1.4.2 Libraries/IP19.1.4.3 Test/Verification19.2 Classification of Embedded Systems19.3 Embedded Processor Architectures19.3.1 RISC and CISC Architectures19.3.2 SISD/SIMD19.3.3 e200z6 Core19.3.4 Cell microprocessor19.3.5 Power PC Architecture19.3.6 1 Overview of PowerPC19.3.6.1 PowerPC family members19.3.6.2 Features of PowerPC 601 (MPC601)19.3.7 PIC16F877 Microcontroller19.3.7.1 Features of PIC16F87719.3.7.2 Pin diagram and block diagram of PIC16F87719.3.7.3 Instruction set of PIC16F87719.3.7.4 Memory organization in PIC16F87719.3.7.5 Assembly language programming of PIC16F87719.3.8 Assembly language programming of PIC16F87719.3.8.1 ARM core Architecture19.3.8.2 Basic ARM Instructions19.3.8.3 Versions of ARM processors and feature19.4 Software Embedded in to System19.4.1 Co design19.5 Bus Architectures19.5.1 Parallel Bus Protocols19.5.2 Serial Bus Protocols19.5.3 Serial Wireless Protocols19.6 Memory19.6.1 Memory Technologies19.6.2 Memory Hierarchy19.6.3 Memory Interfacing19.6 I/O Interfacing19.7 Smart Card Design19.8.1 Vertical (Concurrent) Codesign19.8.2 Horizontal (Serial) Codesign19.8.3 Security Extension20. Hybrid Programming Techniques Using AMS and C/C++20.1 Combining ASSEMBLY LANGUAGE WITH C/C++20.2 Calling Conventions20.2.1 CDECL calling convention20.2.2 STDCALL calling convention20.2.3 FASTCALL calling convention20.3 Passing Parameter Techniques20.4 Techniques for 16 Bit ALP Microsoft C/C++ for DOS.20.4.1 Inline Assembly20.4.2 Linked assembly20.5 Using ALP with C/C++ for 32-Bit Applications20.6 32-Bit Windows Programming20.6.1 Consol functions20.6.2 Win32 Application Programming Interface (API).20.7 Program Development Methods20.7.1 graphical User Interface20.7.2 Creating the Hybrid _prj Project ( MSVC6.0)20.7.3 Creating the Hybrid _prj Project (using Microsoft Visual Studio)Appendix A: 8085 Instruction SetAppendix B: 8051 Instruction SetAppendix C: 8086 Instruction SetAppendix D: 8096 Instruction SetAppendix E: Case studiesAppendix F: Multiple choice questions on 8085, 8086 and 8051Bibliography